diff options
author | Derek Hower <drh5@cs.wisc.edu> | 2010-01-19 17:11:36 -0600 |
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committer | Derek Hower <drh5@cs.wisc.edu> | 2010-01-19 17:11:36 -0600 |
commit | 07ea0891f1699f6194a05516948ce3824fb8fb38 (patch) | |
tree | b5c22e3fe49a7e0d277fdb9ac5ee87c2aa0321e5 /src/mem/ruby/config | |
parent | 279f179babc9e5663156777c533c06edc91bce9a (diff) | |
download | gem5-07ea0891f1699f6194a05516948ce3824fb8fb38.tar.xz |
ruby: new atomics implementation
This patch changes the way that Ruby handles atomic RMW instructions. This implementation, unlike the prior one, is protocol independent. It works by locking an address from the sequencer immediately after the read portion of an RMW completes. When that address is locked, the coherence controller will only satisfy requests coming from one port (e.g., the mandatory queue) and will ignore all others. After the write portion completed, the line is unlocked. This should also work with multi-line atomics, as long as the blocks are always acquired in the same order.
Diffstat (limited to 'src/mem/ruby/config')
-rw-r--r-- | src/mem/ruby/config/MI_example-homogeneous.rb | 2 | ||||
-rw-r--r-- | src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb | 6 | ||||
-rw-r--r-- | src/mem/ruby/config/cfg.rb | 12 |
3 files changed, 10 insertions, 10 deletions
diff --git a/src/mem/ruby/config/MI_example-homogeneous.rb b/src/mem/ruby/config/MI_example-homogeneous.rb index 71e20c318..d409e6782 100644 --- a/src/mem/ruby/config/MI_example-homogeneous.rb +++ b/src/mem/ruby/config/MI_example-homogeneous.rb @@ -13,7 +13,7 @@ RubySystem.reset # default values num_cores = 2 -l1_cache_size_kb = 32768 +l1_cache_size_bytes = 32768 l1_cache_assoc = 8 l1_cache_latency = 1 num_memories = 2 diff --git a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb index a8ef1eceb..ee22df656 100644 --- a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb +++ b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb @@ -68,8 +68,8 @@ assert((protocol == "MESI_CMP_directory" or protocol == "MOESI_CMP_directory"), require protocol+".rb" num_cores.times { |n| - icache = SetAssociativeCache.new("l1i_"+n.to_s, l1_icache_size_kb, l1_icache_latency, l1_icache_assoc, "PSEUDO_LRU") - dcache = SetAssociativeCache.new("l1d_"+n.to_s, l1_dcache_size_kb, l1_dcache_latency, l1_dcache_assoc, "PSEUDO_LRU") + icache = SetAssociativeCache.new("l1i_"+n.to_s, l1_icache_size_kb*1024, l1_icache_latency, l1_icache_assoc, "PSEUDO_LRU") + dcache = SetAssociativeCache.new("l1d_"+n.to_s, l1_dcache_size_kb*1024, l1_dcache_latency, l1_dcache_assoc, "PSEUDO_LRU") sequencer = Sequencer.new("Sequencer_"+n.to_s, icache, dcache) iface_ports << sequencer if protocol == "MOESI_CMP_directory" @@ -87,7 +87,7 @@ num_cores.times { |n| end } num_l2_banks.times { |n| - cache = SetAssociativeCache.new("l2u_"+n.to_s, l2_cache_size_kb/num_l2_banks, l2_cache_latency, l2_cache_assoc, "PSEUDO_LRU") + cache = SetAssociativeCache.new("l2u_"+n.to_s, (l2_cache_size_kb*1024)/num_l2_banks, l2_cache_latency, l2_cache_assoc, "PSEUDO_LRU") if protocol == "MOESI_CMP_directory" net_ports << MOESI_CMP_directory_L2CacheController.new("L2CacheController_"+n.to_s, "L2Cache", diff --git a/src/mem/ruby/config/cfg.rb b/src/mem/ruby/config/cfg.rb index d57862420..a20562243 100644 --- a/src/mem/ruby/config/cfg.rb +++ b/src/mem/ruby/config/cfg.rb @@ -385,12 +385,12 @@ class DMAController < NetPort end class Cache < LibRubyObject - param :size_kb, Integer + param :size, Integer param :latency, Integer param :controller, NetPort - def initialize(obj_name, size_kb, latency) + def initialize(obj_name, size, latency) super(obj_name) - self.size_kb = size_kb + self.size = size self.latency = latency # controller must be set manually by the configuration script # because there is a cyclic dependence @@ -406,8 +406,8 @@ class SetAssociativeCache < Cache # when an integer, it represents the number of cycles for a hit # when a float, it represents the cache access time in ns # when set to "auto", libruby will attempt to find a realistic latency by running CACTI - def initialize(obj_name, size_kb, latency, assoc, replacement_policy) - super(obj_name, size_kb, latency) + def initialize(obj_name, size, latency, assoc, replacement_policy) + super(obj_name, size, latency) self.assoc = assoc self.replacement_policy = replacement_policy end @@ -415,7 +415,7 @@ class SetAssociativeCache < Cache def calculateLatency() if self.latency == "auto" cacti_args = Array.new() - cacti_args << (self.size_kb*1024) << RubySystem.block_size_bytes << self.assoc + cacti_args << (self.size*1024) << RubySystem.block_size_bytes << self.assoc cacti_args << 1 << 0 << 0 << 0 << 1 cacti_args << RubySystem.tech_nm << RubySystem.block_size_bytes*8 cacti_args << 0 << 0 << 0 << 1 << 0 << 0 << 0 << 0 << 1 |