merge

6 files changed, 254 insertions, 5 deletions

diff --git a/src/mem/ruby/config/MI_example-homogeneous.rb b/src/mem/ruby/config/MI_example-homogeneous.rb
index 409d0fe3a..71e20c318 100644
--- a/src/mem/ruby/config/MI_example-homogeneous.rb
+++ b/src/mem/ruby/config/MI_example-homogeneous.rb
@@ -13,7 +13,7 @@ RubySystem.reset
 # default values
 
 num_cores = 2
-l1_cache_size_kb = 32
+l1_cache_size_kb = 32768
 l1_cache_assoc = 8
 l1_cache_latency = 1
 num_memories = 2
@@ -44,6 +44,15 @@ for i in 0..$*.size-1 do
   elsif $*[i] == "-s"
     memory_size_mb = $*[i+1].to_i
     i = i + 1
+  elsif $*[i] == "-C"
+    l1_cache_size_bytes = $*[i+1].to_i
+    i = i + 1
+  elsif $*[i] == "-A"
+    l1_cache_assoc = $*[i+1].to_i
+    i = i + 1
+  elsif $*[i] == "-D"
+    num_dma = $*[i+1].to_i
+    i = i + 1
   end
 end
 
@@ -55,7 +64,7 @@ assert(protocol == "MI_example", __FILE__ + " cannot be used with protocol " + p
 require protocol+".rb"
 
 num_cores.times { |n|
-  cache = SetAssociativeCache.new("l1u_"+n.to_s, l1_cache_size_kb, l1_cache_latency, l1_cache_assoc, "PSEUDO_LRU")
+  cache = SetAssociativeCache.new("l1u_"+n.to_s, l1_cache_size_bytes, l1_cache_latency, l1_cache_assoc, "PSEUDO_LRU")
   sequencer = Sequencer.new("Sequencer_"+n.to_s, cache, cache)
   iface_ports << sequencer
   net_ports << MI_example_CacheController.new("L1CacheController_"+n.to_s,
diff --git a/src/mem/ruby/config/MI_example.rb b/src/mem/ruby/config/MI_example.rb
index 187dc7a68..8113087aa 100644
--- a/src/mem/ruby/config/MI_example.rb
+++ b/src/mem/ruby/config/MI_example.rb
@@ -23,8 +23,6 @@ class MI_example_DirectoryController < DirectoryController
   def argv()
     vec = super()
     vec += " directory_latency "+directory_latency.to_s
-    vec += " dma_select_low_bit "+log_int(RubySystem.block_size_bytes).to_s
-    vec += " dma_select_num_bits "+log_int(NetPort.totalOfType("DMA")).to_s
   end
 end
 
diff --git a/src/mem/ruby/config/MOESI_CMP_token.rb b/src/mem/ruby/config/MOESI_CMP_token.rb
new file mode 100644
index 000000000..ba963dc06
--- /dev/null
+++ b/src/mem/ruby/config/MOESI_CMP_token.rb
@@ -0,0 +1,92 @@
+
+require "cfg.rb"
+require "util.rb"
+
+
+class MOESI_CMP_token_L1CacheController < L1CacheController
+  attr :icache, :dcache
+  attr :num_l2_controllers
+  attr :n_tokens
+  def initialize(obj_name, mach_type, icache, dcache, sequencer, num_l2_controllers, n_tokens)
+    super(obj_name, mach_type, [icache, dcache], sequencer)
+    @icache = icache
+    @dcache = dcache
+    @num_l2_controllers = num_l2_controllers
+    @n_tokens = n_tokens
+  end
+  def argv()
+    num_select_bits = log_int(num_l2_controllers)
+    num_block_bits = log_int(RubySystem.block_size_bytes)
+
+    l2_select_low_bit = num_block_bits
+
+    vec = super()
+    vec += " icache " + @icache.obj_name
+    vec += " dcache " + @dcache.obj_name
+    vec += " l1_request_latency " + l1_request_latency.to_s
+    vec += " l1_response_latency " + l1_response_latency.to_s
+    vec += " l2_select_low_bit " + l2_select_low_bit.to_s
+    vec += " l2_select_num_bits " + num_select_bits.to_s
+    vec += " N_tokens " + n_tokens.to_s
+    vec += " retry_threshold " + retry_threshold.to_s
+    vec += " fixed_timeout_latency " + fixed_timeout_latency.to_s
+    vec += " dynamic_timeout_enabled " + dynamic_timeout_enabled.to_s
+
+    return vec
+  end
+end
+
+class MOESI_CMP_token_L2CacheController < CacheController
+  attr :cache
+  attr :n_tokens
+  def initialize(obj_name, mach_type, cache, n_tokens)
+    super(obj_name, mach_type, [cache])
+    @cache = cache
+    @n_tokens = n_tokens
+  end
+  def argv()
+    vec = super()
+    vec += " cache " + @cache.obj_name
+    vec += " l2_request_latency " + l2_request_latency.to_s
+    vec += " l2_response_latency " + l2_response_latency.to_s
+    vec += " N_tokens " + n_tokens.to_s
+    vec += " filtering_enabled " + filtering_enabled.to_s
+    return vec
+  end
+end
+
+
+class MOESI_CMP_token_DirectoryController < DirectoryController
+  attr :num_l2_controllers
+  def initialize(obj_name, mach_type, directory, memory_control, num_l2_controllers)
+    super(obj_name, mach_type, directory, memory_control)
+    @num_l2_controllers = num_l2_controllers
+  end
+  def argv()
+    num_select_bits = log_int(num_l2_controllers)
+    num_block_bits = log_int(RubySystem.block_size_bytes)
+
+    l2_select_low_bit = num_block_bits
+
+    vec = super()
+    vec += " directory_latency "+directory_latency.to_s
+    vec += " l2_select_low_bit " + l2_select_low_bit.to_s
+    vec += " l2_select_num_bits " + num_select_bits.to_s
+    vec += " distributed_persistent "+distributed_persistent.to_s
+    vec += " fixed_timeout_latency " + fixed_timeout_latency.to_s
+    return vec
+  end
+
+end
+
+class MOESI_CMP_token_DMAController < DMAController
+  def initialize(obj_name, mach_type, dma_sequencer)
+    super(obj_name, mach_type, dma_sequencer)
+  end
+  def argv()
+    vec = super
+    vec += " request_latency "+request_latency.to_s
+    vec += " response_latency "+response_latency.to_s
+    return vec
+  end
+end
diff --git a/src/mem/ruby/config/MOESI_hammer-homogeneous.rb b/src/mem/ruby/config/MOESI_hammer-homogeneous.rb
new file mode 100644
index 000000000..02af0ec27
--- /dev/null
+++ b/src/mem/ruby/config/MOESI_hammer-homogeneous.rb
@@ -0,0 +1,109 @@
+#!/usr/bin/ruby
+#
+#  Creates multiple on-chip nodes with three level of cache.
+#
+
+require "cfg.rb"
+
+RubySystem.reset
+
+# default values
+
+num_cores = 2
+l1_cache_size_bytes = 32768
+l1_cache_assoc = 2
+l1_cache_latency = 3
+l2_cache_size_bytes = 1048576
+l2_cache_assoc = 16
+l2_cache_latency = 15
+num_memories = 2
+memory_size_mb = 1024
+num_dma = 0
+use_map = false
+map_levels = 4
+protocol = "MOESI_hammer"
+
+# check for overrides
+
+
+for i in 0..$*.size-1 do
+  if $*[i] == "-c"
+    protocol = $*[i+1]
+    i = i+1
+  elsif $*[i] == "-p"
+    num_cores = $*[i+1].to_i
+    i = i+1
+  elsif $*[i] == "-m"
+    num_memories = $*[i+1].to_i
+    i = i+1
+  elsif $*[i] == "-s"
+    memory_size_mb = $*[i+1].to_i
+    i = i + 1
+  elsif $*[i] == "-U"
+    use_map = $*[i+1]
+    i = i + 1
+  elsif $*[i] == "-C"
+    l1_cache_size_bytes = $*[i+1].to_i
+    i = i + 1
+  elsif $*[i] == "-A"
+    l1_cache_assoc = $*[i+1].to_i
+    i = i + 1
+  elsif $*[i] == "-M"
+    map_levels = $*[i+1].to_i
+    i = i + 1
+  elsif $*[i] == "-D"
+    num_dma = $*[i+1].to_i
+    i = i + 1
+  end
+end
+
+net_ports = Array.new
+iface_ports = Array.new
+
+assert(protocol == "MOESI_hammer", __FILE__ + " cannot be used with protocol " + protocol)
+
+require protocol+".rb"
+
+num_cores.times { |n|
+  icache = SetAssociativeCache.new("l1i_"+n.to_s, 
+                                   l1_cache_size_bytes, 
+                                   l1_cache_latency, 
+                                   l1_cache_assoc, 
+                                   "PSEUDO_LRU")
+  dcache = SetAssociativeCache.new("l1d_"+n.to_s, 
+                                   l1_cache_size_bytes, 
+                                   l1_cache_latency, 
+                                   l1_cache_assoc, 
+                                   "PSEUDO_LRU")
+  l2cache = SetAssociativeCache.new("l2u_"+n.to_s, 
+                                    l2_cache_size_bytes, 
+                                    l2_cache_latency, 
+                                    l2_cache_assoc, 
+                                    "PSEUDO_LRU")
+  sequencer = Sequencer.new("Sequencer_"+n.to_s, icache, dcache)
+  iface_ports << sequencer
+  net_ports << MOESI_hammer_CacheController.new("L1CacheController_"+n.to_s,
+                                                "L1Cache",
+                                                icache,
+                                                dcache,
+                                                l2cache,
+                                                sequencer)
+}
+num_memories.times { |n|
+  directory = DirectoryMemory.new("DirectoryMemory_"+n.to_s, memory_size_mb/num_memories)
+  memory_control = MemoryControl.new("MemoryControl_"+n.to_s)
+  net_ports << MOESI_hammer_DirectoryController.new("DirectoryController_"+n.to_s,
+                                                    "Directory",
+                                                    directory, 
+                                                    memory_control)
+}
+num_dma.times { |n|
+  dma_sequencer = DMASequencer.new("DMASequencer_"+n.to_s)
+  iface_ports << dma_sequencer
+  net_ports << MOESI_hammer_DMAController.new("DMAController_"+n.to_s, "DMA", dma_sequencer)
+}
+
+topology = CrossbarTopology.new("theTopology", net_ports)
+on_chip_net = Network.new("theNetwork", topology)
+
+RubySystem.init(iface_ports, on_chip_net)
diff --git a/src/mem/ruby/config/MOESI_hammer.rb b/src/mem/ruby/config/MOESI_hammer.rb
new file mode 100644
index 000000000..d3735028b
--- /dev/null
+++ b/src/mem/ruby/config/MOESI_hammer.rb
@@ -0,0 +1,41 @@
+
+require "util.rb"
+
+class MOESI_hammer_CacheController < L1CacheController
+  attr :cache
+  def initialize(obj_name, mach_type, icache, dcache, l2cache, sequencer)
+    super(obj_name, mach_type, [icache, dcache, l2cache], sequencer)
+    @icache = icache
+    @dcache = dcache
+    @l2cache = l2cache
+  end
+  def argv()
+    vec = super()
+    vec += " icache " + @icache.obj_name
+    vec += " dcache " + @dcache.obj_name
+    vec += " l2cache " + @l2cache.obj_name
+    vec += " issue_latency "+issue_latency.to_s
+    vec += " cache_response_latency "+cache_response_latency.to_s
+  end
+
+end
+
+class MOESI_hammer_DirectoryController < DirectoryController
+  def initialize(obj_name, mach_type, directory, memory_control)
+    super(obj_name, mach_type, directory, memory_control)
+  end
+  def argv()
+    vec = super()
+    vec += " memory_controller_latency "+memory_controller_latency.to_s
+  end
+end
+
+class MOESI_hammer_DMAController < DMAController
+  def initialize(obj_name, mach_type, dma_sequencer)
+    super(obj_name, mach_type, dma_sequencer)
+  end
+  def argv()
+    vec = super
+    vec += " request_latency "+request_latency.to_s
+  end
+end
diff --git a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
index a4a1982f4..a8ef1eceb 100644
--- a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
+++ b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
@@ -27,7 +27,7 @@ memory_size_mb = 1024
 num_dma = 1
 
 #default protocol 
-protocol = ""#"MESI_CMP_directory"
+protocol = "MOESI_CMP_directory"
 
 # check for overrides