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authorBrad Beckmann <Brad.Beckmann@amd.com>2011-04-28 17:18:14 -0700
committerBrad Beckmann <Brad.Beckmann@amd.com>2011-04-28 17:18:14 -0700
commit40bcbf42539fec83628f2ae2627238adff27f62c (patch)
tree993083e3b6e5661697261e81869bf40e17027826 /src/mem/ruby/network/BasicLink.hh
parentbc5eb596053f7f69c88f8218f20709d94b2a331c (diff)
downloadgem5-40bcbf42539fec83628f2ae2627238adff27f62c.tar.xz
network: convert links & switches to first class C++ SimObjects
This patch converts links and switches from second class simobjects that were virtually ignored by the networks (both simple and Garnet) to first class simobjects that directly correspond to c++ ojbects manipulated by the topology and network classes. This is especially true for Garnet, where the links and switches directly correspond to specific C++ objects. By making this change, many aspects of the Topology class were simplified. --HG-- rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/BasicLink.cc rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/BasicLink.hh rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.cc rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.cc rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
Diffstat (limited to 'src/mem/ruby/network/BasicLink.hh')
-rw-r--r--src/mem/ruby/network/BasicLink.hh96
1 files changed, 96 insertions, 0 deletions
diff --git a/src/mem/ruby/network/BasicLink.hh b/src/mem/ruby/network/BasicLink.hh
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+++ b/src/mem/ruby/network/BasicLink.hh
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+/*
+ * Copyright (c) 2011 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MEM_RUBY_NETWORK_BASIC_LINK_HH__
+#define __MEM_RUBY_NETWORK_BASIC_LINK_HH__
+
+#include <iostream>
+#include <string>
+#include <vector>
+
+#include "params/BasicExtLink.hh"
+#include "params/BasicIntLink.hh"
+#include "params/BasicLink.hh"
+#include "mem/ruby/network/BasicRouter.hh"
+#include "mem/ruby/network/Topology.hh"
+#include "mem/ruby/slicc_interface/AbstractController.hh"
+#include "sim/sim_object.hh"
+
+class BasicLink : public SimObject
+{
+ public:
+ typedef BasicLinkParams Params;
+ BasicLink(const Params *p);
+ const Params *params() const { return (const Params *)_params; }
+
+ void init();
+
+ void print(std::ostream& out) const;
+
+ int m_latency;
+ int m_bw_multiplier;
+ int m_weight;
+};
+
+inline std::ostream&
+operator<<(std::ostream& out, const BasicLink& obj)
+{
+ obj.print(out);
+ out << std::flush;
+ return out;
+}
+
+class BasicExtLink : public BasicLink
+{
+ public:
+ typedef BasicExtLinkParams Params;
+ BasicExtLink(const Params *p);
+ const Params *params() const { return (const Params *)_params; }
+
+ friend class Topology;
+
+ protected:
+ BasicRouter* m_int_node;
+ AbstractController* m_ext_node;
+};
+
+class BasicIntLink : public BasicLink
+{
+ public:
+ typedef BasicIntLinkParams Params;
+ BasicIntLink(const Params *p);
+ const Params *params() const { return (const Params *)_params; }
+
+ friend class Topology;
+
+ protected:
+ BasicRouter* m_node_a;
+ BasicRouter* m_node_b;
+};
+
+#endif // __MEM_RUBY_NETWORK_BASIC_LINK_HH__