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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-04-29 22:35:22 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-04-29 22:35:22 -0500 |
| commit | 0dbd696aaef47205c1430b53841423c7d25455ed (patch) | |
| tree | eada915ea9c506520042b57a1d011ec3fe18a149 /src/mem/ruby/network/MessageBuffer.hh | |
| parent | ee06fed656d404c19c68c838df1dc8dbba37ec80 (diff) | |
| download | gem5-0dbd696aaef47205c1430b53841423c7d25455ed.tar.xz | |
cpu: o3: single cycle default div microop latency on x86
This patch sets the default latency of the division microop to a single cycle
on x86. This is because the division instructions DIV and IDIV have been
implemented as loops of div microops, where each microop computes a single bit
of the quotient.
Diffstat (limited to 'src/mem/ruby/network/MessageBuffer.hh')
0 files changed, 0 insertions, 0 deletions