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author | David Hashe <david.hashe@amd.com> | 2015-07-20 09:15:18 -0500 |
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committer | David Hashe <david.hashe@amd.com> | 2015-07-20 09:15:18 -0500 |
commit | 0d00cbc97b47344e12e9eb943efb9ca29db66898 (patch) | |
tree | 705c0b835f10b1f910b9753b96d07ee8b474f4f9 /src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc | |
parent | 8b32dad4d8545bf33285853936ede834cb39cf77 (diff) | |
download | gem5-0d00cbc97b47344e12e9eb943efb9ca29db66898.tar.xz |
ruby: change router pipeline stages to 2
This patch changes the router pipeline stages from 4 to 2. The
canonical 4-stage router is conservative while a lower-latency router
with look ahead routing and speculative allocation is well acknowledged.
Diffstat (limited to 'src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc')
-rw-r--r-- | src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc index fb147babc..2f99d387a 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc @@ -81,8 +81,14 @@ InputUnit_d::wakeup() m_vcs[vc]->set_enqueue_time(m_router->curCycle()); } else { - t_flit->advance_stage(SA_, m_router->curCycle() + Cycles(1)); - m_router->swarb_req(); + t_flit->advance_stage(SA_, m_router->curCycle()); + // Changing router latency to 2 cycles. Input Unit takes 1 cycle for wakeup. + // VCalloc, SWalloc, Sw-Xfer and output scheduling takes 1 cycle. The original + // design schedules VCallocator for head flit, and Swalloc for non-head flit. + // VCalloc now calls SWalloc directly instead of scheduling it for the next cycle, + // hence we should not allocate SWalloc, otherwise it might get called twice, once + // by the scheduler and once by VCalloc. + m_router->vcarb_req(); } // write flit into input buffer m_vcs[vc]->insertFlit(t_flit); |