diff options
author | David Hashe <david.hashe@amd.com> | 2015-07-20 09:15:18 -0500 |
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committer | David Hashe <david.hashe@amd.com> | 2015-07-20 09:15:18 -0500 |
commit | 0d00cbc97b47344e12e9eb943efb9ca29db66898 (patch) | |
tree | 705c0b835f10b1f910b9753b96d07ee8b474f4f9 /src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc | |
parent | 8b32dad4d8545bf33285853936ede834cb39cf77 (diff) | |
download | gem5-0d00cbc97b47344e12e9eb943efb9ca29db66898.tar.xz |
ruby: change router pipeline stages to 2
This patch changes the router pipeline stages from 4 to 2. The
canonical 4-stage router is conservative while a lower-latency router
with look ahead routing and speculative allocation is well acknowledged.
Diffstat (limited to 'src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc')
-rw-r--r-- | src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc index 21fbfe6e5..1e636b589 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/SWallocator_d.cc @@ -82,6 +82,7 @@ SWallocator_d::wakeup() clear_request_vector(); check_for_wakeup(); + m_router->call_switch(); } @@ -178,10 +179,10 @@ SWallocator_d::arbitrate_outports() // remove flit from Input Unit flit_d *t_flit = m_input_unit[inport]->getTopFlit(invc); - t_flit->advance_stage(ST_, m_router->curCycle() + Cycles(1)); + t_flit->advance_stage(ST_, m_router->curCycle()); t_flit->set_vc(outvc); t_flit->set_outport(outport); - t_flit->set_time(m_router->curCycle() + Cycles(1)); + t_flit->set_time(m_router->curCycle()); m_output_unit[outport]->decrement_credit(outvc); m_router->update_sw_winner(inport, t_flit); @@ -223,7 +224,7 @@ SWallocator_d::check_for_wakeup() for (int i = 0; i < m_num_inports; i++) { for (int j = 0; j < m_num_vcs; j++) { if (m_input_unit[i]->need_stage(j, ACTIVE_, SA_, nextCycle)) { - scheduleEvent(Cycles(1)); + m_router->vcarb_req(); return; } } |