diff options
author | Tushar Krishna <tushar@csail.mit.edu> | 2011-02-06 22:14:17 -0800 |
---|---|---|
committer | Tushar Krishna <tushar@csail.mit.edu> | 2011-02-06 22:14:17 -0800 |
commit | a679e732cee821616c20cc13c22ad2877072ff14 (patch) | |
tree | d3225f0f3bc7f4f79fa3eeb7bf0fb40de19509aa /src/mem/ruby/network/orion/Buffer | |
parent | 59163f824c71e4290399be7c1c4b6e70b799a388 (diff) | |
download | gem5-a679e732cee821616c20cc13c22ad2877072ff14.tar.xz |
garnet: added orion2.0 for network power calculation
Diffstat (limited to 'src/mem/ruby/network/orion/Buffer')
21 files changed, 2538 insertions, 0 deletions
diff --git a/src/mem/ruby/network/orion/Buffer/AmpUnit.cc b/src/mem/ruby/network/orion/Buffer/AmpUnit.cc new file mode 100644 index 000000000..f6be2fe52 --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/AmpUnit.cc @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2009 Princeton University, and + * Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Hangsheng Wang (Orion 1.0, Princeton) + * Xinping Zhu (Orion 1.0, Princeton) + * Xuning Chen (Orion 1.0, Princeton) + * Bin Li (Orion 2.0, Princeton) + * Kambiz Samadi (Orion 2.0, UC San Diego) + */ + +#include "mem/ruby/network/orion/Buffer/AmpUnit.hh" +#include "mem/ruby/network/orion/TechParameter.hh" + +AmpUnit::AmpUnit( + const string& amp_model_str_, + const TechParameter* tech_param_ptr_ + ) +{ + if (amp_model_str_.compare("GENERIC_AMP") == 0) + { + m_amp_model = GENERIC_AMP; + } + else + { + m_amp_model = NO_MODEL; + } + + if (m_amp_model != NO_MODEL) + { + m_tech_param_ptr = tech_param_ptr_; + + init(); + } +} + +AmpUnit::~AmpUnit() +{} + +void AmpUnit::init() +{ + double vdd = m_tech_param_ptr->get_vdd(); + double period = m_tech_param_ptr->get_period(); + double amp_Idsat = m_tech_param_ptr->get_amp_idsat(); + + m_e_access = (vdd / 8.0 * period * amp_Idsat); + return; +} diff --git a/src/mem/ruby/network/orion/Buffer/AmpUnit.hh b/src/mem/ruby/network/orion/Buffer/AmpUnit.hh new file mode 100644 index 000000000..30c4cd0ec --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/AmpUnit.hh @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2009 Princeton University, and + * Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Hangsheng Wang (Orion 1.0, Princeton) + * Xinping Zhu (Orion 1.0, Princeton) + * Xuning Chen (Orion 1.0, Princeton) + * Bin Li (Orion 2.0, Princeton) + * Kambiz Samadi (Orion 2.0, UC San Diego) + */ + +#ifndef __AMPUNIT_H__ +#define __AMPUNIT_H__ + +#include "mem/ruby/network/orion/Type.hh" + +class TechParameter; + +class AmpUnit +{ + public: + enum AmpModel + { + NO_MODEL = 0, + GENERIC_AMP + }; + + public: + AmpUnit( + const string& amp_model_str_, + const TechParameter* tech_param_ptr_ + ); + ~AmpUnit(); + + public: + double get_e_access() const { return m_e_access; } + + private: + void init(); + + private: + AmpModel m_amp_model; + const TechParameter* m_tech_param_ptr; + + double m_e_access; +}; + +#endif + diff --git a/src/mem/ruby/network/orion/Buffer/BitlineUnit.cc b/src/mem/ruby/network/orion/Buffer/BitlineUnit.cc new file mode 100644 index 000000000..05d0ae382 --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/BitlineUnit.cc @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2009 Princeton University, and + * Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Hangsheng Wang (Orion 1.0, Princeton) + * Xinping Zhu (Orion 1.0, Princeton) + * Xuning Chen (Orion 1.0, Princeton) + * Bin Li (Orion 2.0, Princeton) + * Kambiz Samadi (Orion 2.0, UC San Diego) + */ + +#include "mem/ruby/network/orion/Buffer/BitlineUnit.hh" +#include "mem/ruby/network/orion/Buffer/SRAM.hh" +#include "mem/ruby/network/orion/TechParameter.hh" + +BitlineUnit::BitlineUnit( + const string bl_model_str_, + const SRAM* sram_ptr_, + const TechParameter* tech_param_ptr_ + ) +{ + if (bl_model_str_ == "RW_BITLINE") + { + m_bl_model = RW_BITLINE; + } + else if (bl_model_str_ == "WO_BITLINE") + { + m_bl_model = WO_BITLINE; + } + else + { + m_bl_model = NO_MODEL; + } + + if (m_bl_model != NO_MODEL) + { + m_sram_ptr = sram_ptr_; + m_tech_param_ptr = tech_param_ptr_; + + init(); + } +} + +BitlineUnit::~BitlineUnit() +{} + +void BitlineUnit::init() +{ + uint32_t num_port = m_sram_ptr->get_num_port(); + uint32_t num_data_end = m_sram_ptr->get_num_data_end(); + double bl_cmetal; + if ((num_port > 1) || (num_data_end == 2)) + { + bl_cmetal = m_tech_param_ptr->get_CC3M2metal(); + } + else + { + bl_cmetal = m_tech_param_ptr->get_CM2metal(); + } + uint32_t num_row = m_sram_ptr->get_num_row(); + double RegCellHeight = m_tech_param_ptr->get_RegCellHeight(); + double WordlineSpacing = m_tech_param_ptr->get_WordlineSpacing(); + m_bl_len = num_row*(RegCellHeight + num_port*WordlineSpacing); + m_bl_wire_cap = m_bl_len * bl_cmetal; + + double e_factor = m_tech_param_ptr->get_EnergyFactor(); + double sense_e_factor = m_tech_param_ptr->get_SenseEnergyFactor(); + switch(m_bl_model) + { + case RW_BITLINE: + if (num_data_end == 2) + { + m_e_col_sel = calc_col_select_cap() * e_factor; + m_e_col_read = calc_col_read_cap() * sense_e_factor; + } + else + { + m_e_col_sel = 0; + m_e_col_read = calc_col_read_cap() * e_factor; + } + m_e_col_write = calc_col_write_cap() * e_factor; + + m_i_static = calc_i_static(); + break; + case WO_BITLINE: + m_e_col_sel = m_e_col_read = 0; + m_e_col_write = calc_col_write_cap() * e_factor; + //FIXME - no static power? + break; + default: + printf("error\n"); + } + return; +} + +double BitlineUnit::calc_col_select_cap() +{ + double Wbitmuxn = m_tech_param_ptr->get_Wbitmuxn(); + return m_tech_param_ptr->calc_gatecap(Wbitmuxn, 1); +} + +double BitlineUnit::calc_col_read_cap() +{ + double total_cap = 0; + + // part 1: drain cap of precharge tx's + //total_cap = m_num_bl_pre * Util::calc_draincap(m_pre_size, Util::PCH, 1); + + // part 2: drain cap of pass tx's + double Wmemcellr = m_tech_param_ptr->get_Wmemcellr(); + uint32_t num_row = m_sram_ptr->get_num_row(); + total_cap = num_row * m_tech_param_ptr->calc_draincap(Wmemcellr, TechParameter::NCH, 1); + + // part 3: metal cap + total_cap += m_bl_wire_cap; + m_pre_unit_load = total_cap; + + // part 4: bitline inverter + uint32_t num_data_end = m_sram_ptr->get_num_data_end(); + if (num_data_end == 1) + { + // FIXME: magic numbers + double MSCALE = m_tech_param_ptr->get_MSCALE(); + total_cap += m_tech_param_ptr->calc_gatecap(MSCALE * (29.9 + 7.8), 0) + m_tech_param_ptr->calc_gatecap(MSCALE * (47.0 + 12.0), 0); + } + + // part 5: gate cap of sense amplifier or output driver + bool is_outdrv = m_sram_ptr->get_is_outdrv(); + if (num_data_end == 2) + { // sense amplifier + double WsenseQ1to4 = m_tech_param_ptr->get_WsenseQ1to4(); + total_cap += 2 * m_tech_param_ptr->calc_gatecap(WsenseQ1to4, 10); + } + else if (is_outdrv) + { + double Woutdrvnandn = m_tech_param_ptr->get_Woutdrvnandn(); + double Woutdrvnandp = m_tech_param_ptr->get_Woutdrvnandp(); + double Woutdrvnorn = m_tech_param_ptr->get_Woutdrvnorn(); + double Woutdrvnorp = m_tech_param_ptr->get_Woutdrvnorp(); + + total_cap += m_tech_param_ptr->calc_gatecap(Woutdrvnandn, 1) + m_tech_param_ptr->calc_gatecap(Woutdrvnandp, 1) + m_tech_param_ptr->calc_gatecap(Woutdrvnorn, 1) + m_tech_param_ptr->calc_gatecap(Woutdrvnorp, 1); + } + + return total_cap; +} + +double BitlineUnit::calc_col_write_cap() +{ + double total_cap, psize, nsize; + + // part 1: line cap, including drain cap of pass tx's and metal cap + uint32_t num_row = m_sram_ptr->get_num_row(); + double Wmemcellw = m_tech_param_ptr->get_Wmemcellw(); + total_cap = num_row * m_tech_param_ptr->calc_draincap(Wmemcellw, TechParameter::NCH, 1) + m_bl_wire_cap; + + // part 2: write driver + double period = m_tech_param_ptr->get_period(); + psize = m_tech_param_ptr->calc_driver_psize(total_cap, period / 8.0); + double Wdecinvn = m_tech_param_ptr->get_Wdecinvn(); + double Wdecinvp = m_tech_param_ptr->get_Wdecinvp(); + nsize = psize * Wdecinvn / Wdecinvp; + total_cap += m_tech_param_ptr->calc_draincap(psize, TechParameter::PCH, 1) + m_tech_param_ptr->calc_draincap(nsize, TechParameter::NCH, 1) + m_tech_param_ptr->calc_gatecap(psize + nsize, 1); + + return total_cap; +} + +double BitlineUnit::calc_i_static() +{ + double Wdecinvn = m_tech_param_ptr->get_Wdecinvn(); + double Wdecinvp = m_tech_param_ptr->get_Wdecinvp(); + double NMOS_TAB_0 = m_tech_param_ptr->get_NMOS_TAB(0); + double PMOS_TAB_0 = m_tech_param_ptr->get_PMOS_TAB(0); + + return (2*(Wdecinvn*NMOS_TAB_0+Wdecinvp*PMOS_TAB_0)); +} diff --git a/src/mem/ruby/network/orion/Buffer/BitlineUnit.hh b/src/mem/ruby/network/orion/Buffer/BitlineUnit.hh new file mode 100644 index 000000000..ffdb33727 --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/BitlineUnit.hh @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2009 Princeton University, and + * Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Hangsheng Wang (Orion 1.0, Princeton) + * Xinping Zhu (Orion 1.0, Princeton) + * Xuning Chen (Orion 1.0, Princeton) + * Bin Li (Orion 2.0, Princeton) + * Kambiz Samadi (Orion 2.0, UC San Diego) + */ + +#ifndef __BITLINEUNIT_H__ +#define __BITLINEUNIT_H__ + +#include "mem/ruby/network/orion/Type.hh" + +class SRAM; +class TechParameter; + +class BitlineUnit +{ + public: + enum BitlineModel + { + NO_MODEL = 0, + RW_BITLINE, + WO_BITLINE + }; + + public: + BitlineUnit( + const string bl_model_str_, + const SRAM* sram_ptr_, + const TechParameter* tech_param_ptr_ + ); + ~BitlineUnit(); + + public: + double get_pre_unit_load() const { return m_pre_unit_load; } + + double get_e_col_read() const { return m_e_col_read; } + double get_e_col_wrtie() const { return m_e_col_write; } + double get_i_static() const { return m_i_static; } + + private: + void init(); + double calc_col_select_cap(); + double calc_col_read_cap(); + double calc_col_write_cap(); + double calc_i_static(); + + private: + BitlineModel m_bl_model; + const SRAM* m_sram_ptr; + const TechParameter* m_tech_param_ptr; + + double m_bl_len; + double m_bl_wire_cap; + double m_pre_unit_load; + + double m_e_col_sel; + double m_e_col_read; + double m_e_col_write; + + double m_i_static; +}; + +#endif + diff --git a/src/mem/ruby/network/orion/Buffer/Buffer.cc b/src/mem/ruby/network/orion/Buffer/Buffer.cc new file mode 100644 index 000000000..11c92094f --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/Buffer.cc @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2009 Princeton University, and + * Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Hangsheng Wang (Orion 1.0, Princeton) + * Xinping Zhu (Orion 1.0, Princeton) + * Xuning Chen (Orion 1.0, Princeton) + * Bin Li (Orion 2.0, Princeton) + * Kambiz Samadi (Orion 2.0, UC San Diego) + */ + +#include <iostream> +#include <cassert> + +#include "mem/ruby/network/orion/Buffer/Buffer.hh" +#include "mem/ruby/network/orion/TechParameter.hh" +#include "mem/ruby/network/orion/OrionConfig.hh" +#include "mem/ruby/network/orion/Buffer/SRAM.hh" +#include "mem/ruby/network/orion/Buffer/Register.hh" + +using namespace std; + +Buffer::Buffer( + const string& buffer_model_str_, + bool is_fifo_, + bool is_outdrv_, + uint32_t num_entry_, + uint32_t line_width_, + uint32_t num_read_port_, + uint32_t num_write_port_, + const OrionConfig* orion_cfg_ptr_ + ) +{ + if (buffer_model_str_ == string("SRAM")) + { + m_buffer_model = BUF_SRAM; + } + else if(buffer_model_str_ == string("REGISTER")) + { + m_buffer_model = BUF_REG; + } + else + { + m_buffer_model = NO_MODEL; + } + + if (m_buffer_model != NO_MODEL) + { + assert(num_entry_ == num_entry_); + assert(line_width_ == line_width_); + assert(num_read_port_ == num_read_port_); + assert(num_write_port_ == num_write_port_); + + m_num_entry = num_entry_; + m_line_width = line_width_; + m_is_fifo = is_fifo_; + m_is_outdrv = is_outdrv_; + m_num_read_port = num_read_port_; + m_num_write_port = num_write_port_; + + m_orion_cfg_ptr = orion_cfg_ptr_; + m_tech_param_ptr = m_orion_cfg_ptr->get_tech_param_ptr(); + + init(); + } +} + +Buffer::~Buffer() +{ + delete m_sram_ptr; +} + +double Buffer::get_dynamic_energy( + bool is_read_, + bool is_max_ + ) const +{ + if (m_buffer_model == BUF_SRAM) + { + if (is_read_) + { + return m_sram_ptr->calc_e_read(is_max_); + } + else + { + return m_sram_ptr->calc_e_write(is_max_); + } + } + else if (m_buffer_model == BUF_REG) + { + if (is_read_) + { + return m_reg_ptr->calc_e_read(); + } + else + { + return m_reg_ptr->calc_e_write(); + } + } + else + { + return 0; + } +} + +double Buffer::get_static_power() const +{ + double vdd = m_tech_param_ptr->get_vdd(); + double SCALE_S = m_tech_param_ptr->get_SCALE_S(); + if (m_buffer_model == BUF_SRAM) + { + return m_sram_ptr->calc_i_static()*vdd*SCALE_S; + } + else if (m_buffer_model == BUF_REG) + { + return m_reg_ptr->calc_i_static()*vdd*SCALE_S; + } + else + { + return 0; + } +} + +void Buffer::print_all() const +{ + cout << "Buffer" << endl; + cout << "\t" << "Read = " << get_dynamic_energy(true, false) << endl; + cout << "\t" << "Write = " << get_dynamic_energy(false, false) << endl; + cout << "\t" << "Static power = " << get_static_power() << endl; + return; +} + +void Buffer::init() +{ + if(m_buffer_model == BUF_SRAM) + { + uint32_t num_data_end = m_orion_cfg_ptr->get<uint32_t>("SRAM_NUM_DATA_END"); + const string& rowdec_model_str = m_orion_cfg_ptr->get<string>("SRAM_ROWDEC_MODEL"); + const string& wl_model_str = m_orion_cfg_ptr->get<string>("SRAM_WORDLINE_MODEL"); + const string& bl_pre_model_str = m_orion_cfg_ptr->get<string>("SRAM_BITLINE_PRE_MODEL"); + const string& mem_model_str = "NORMAL_MEM"; + const string& bl_model_str = m_orion_cfg_ptr->get<string>("SRAM_BITLINE_MODEL"); + const string& amp_model_str = m_orion_cfg_ptr->get<string>("SRAM_AMP_MODEL"); + const string& outdrv_model_str = m_orion_cfg_ptr->get<string>("SRAM_OUTDRV_MODEL"); + m_sram_ptr = new SRAM( + m_num_entry, m_line_width, m_is_fifo, m_is_outdrv, + m_num_read_port, m_num_write_port, num_data_end, + rowdec_model_str, wl_model_str, bl_pre_model_str, mem_model_str, + bl_model_str, amp_model_str, outdrv_model_str, m_tech_param_ptr); + } + else if (m_buffer_model == BUF_REG) + { + m_sram_ptr = NULL; + m_reg_ptr = new Register(m_num_entry, m_line_width, m_tech_param_ptr); + } + else + { + m_sram_ptr = NULL; + m_reg_ptr = NULL; + } + return; +} + diff --git a/src/mem/ruby/network/orion/Buffer/Buffer.hh b/src/mem/ruby/network/orion/Buffer/Buffer.hh new file mode 100644 index 000000000..cf61bee2b --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/Buffer.hh @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2009 Princeton University, and + * Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Hangsheng Wang (Orion 1.0, Princeton) + * Xinping Zhu (Orion 1.0, Princeton) + * Xuning Chen (Orion 1.0, Princeton) + * Bin Li (Orion 2.0, Princeton) + * Kambiz Samadi (Orion 2.0, UC San Diego) + */ + +#ifndef __BUFFER_H__ +#define __BUFFER_H__ + +#include "mem/ruby/network/orion/Type.hh" + +class OrionConfig; +class TechParameter; + +class SRAM; +class Register; + +class Buffer +{ + public: + enum BufferModel + { + NO_MODEL = 0, + BUF_SRAM, + BUF_REG + }; + + public: + Buffer( + const string& buffer_model_str_, + bool is_fifo_, + bool is_outdrv_, + uint32_t num_entry_, + uint32_t line_width_, + uint32_t num_read_port_, + uint32_t num_write_port_, + const OrionConfig* orion_cfg_ptr_ + ); + ~Buffer(); + + public: + double get_dynamic_energy(bool is_read_, bool is_max_) const; + double get_static_power() const; + + void print_all() const; + + private: + void init(); + + private: + BufferModel m_buffer_model; + uint32_t m_num_entry; + uint32_t m_line_width; + + bool m_is_fifo; + bool m_is_outdrv; + uint32_t m_num_read_port; + uint32_t m_num_write_port; + const OrionConfig* m_orion_cfg_ptr; + const TechParameter* m_tech_param_ptr; + + SRAM* m_sram_ptr; + Register* m_reg_ptr; +}; + +#endif + diff --git a/src/mem/ruby/network/orion/Buffer/DecoderUnit.cc b/src/mem/ruby/network/orion/Buffer/DecoderUnit.cc new file mode 100644 index 000000000..101efdf5e --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/DecoderUnit.cc @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2009 Princeton University, and + * Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Hangsheng Wang (Orion 1.0, Princeton) + * Xinping Zhu (Orion 1.0, Princeton) + * Xuning Chen (Orion 1.0, Princeton) + * Bin Li (Orion 2.0, Princeton) + * Kambiz Samadi (Orion 2.0, UC San Diego) + */ + +#include <cmath> + +#include "mem/ruby/network/orion/Buffer/DecoderUnit.hh" +#include "mem/ruby/network/orion/TechParameter.hh" + +using namespace std; + +DecoderUnit::DecoderUnit( + const string& dec_model_str_, + uint32_t dec_width_, + const TechParameter* tech_param_ptr_ + ) +{ + if (dec_model_str_.compare("GENERIC_DEC") == 0) + { + m_dec_model = GENERIC_DEC; + } + else + { + m_dec_model = NO_MODEL; + } + + if (m_dec_model != NO_MODEL) + { + m_dec_width = dec_width_; + m_tech_param_ptr = tech_param_ptr_; + + init(); + } +} + +DecoderUnit::~DecoderUnit() +{ +} + +void DecoderUnit::init() +{ + if (m_dec_width >= 4) + { // 2-level decoder + m_num_in_1st = (m_dec_width == 4)? 2:3; + m_num_out_0th = 1 << (m_num_in_1st - 1); + m_num_in_2nd = (uint32_t)ceil((double)m_dec_width/(double)m_num_in_1st); + m_num_out_1st = 1 << (m_dec_width - m_num_in_1st); + } + else if (m_dec_width >= 2) + { // 1-level decoder + m_num_in_1st = m_dec_width; + m_num_out_0th = 1 << (m_num_in_1st - 1); + m_num_in_2nd = m_num_out_1st = 0; + } + else + { + m_num_in_1st = m_num_out_0th = m_num_in_2nd = m_num_out_1st = 0; + } + + // compute energy constants + double e_factor = m_tech_param_ptr->get_vdd() * m_tech_param_ptr->get_vdd(); + if (m_dec_width >= 4) + { + m_e_chg_l1 = calc_chgl1_cap() * e_factor; + m_e_chg_output = calc_select_cap() * e_factor; + } + else if (m_dec_width >= 2) + { + m_e_chg_l1 = calc_chgl1_cap() * e_factor; + m_e_chg_output = 0; + } + else + { + m_e_chg_l1 = m_e_chg_output = 0; + } + m_e_chg_addr = calc_chgaddr_cap() * e_factor; + + return; +} + +double DecoderUnit::calc_chgl1_cap() +{ + double total_cap; + + // part 1: drain cap of level-1 decoder + double Wdec3to8p = m_tech_param_ptr->get_Wdec3to8p(); + double Wdec3to8n = m_tech_param_ptr->get_Wdec3to8n(); + total_cap = m_num_in_1st * m_tech_param_ptr->calc_draincap(Wdec3to8p, TechParameter::PCH, 1) + m_tech_param_ptr->calc_draincap(Wdec3to8n, TechParameter::NCH, m_num_in_1st); + + /* part 2: gate cap of level-2 decoder */ + /* WHS: 40 and 20 should go to PARM */ + double WdecNORn = m_tech_param_ptr->get_WdecNORn(); + double WdecNORp = m_tech_param_ptr->get_WdecNORp(); + total_cap += m_num_out_0th*m_tech_param_ptr->calc_gatecap((WdecNORn+WdecNORp), m_num_in_2nd*40 + 20); + + return total_cap; +} + +double DecoderUnit::calc_select_cap() +{ + double total_cap; + + // part 1: drain cap of last level decoders + double WdecNORp = m_tech_param_ptr->get_WdecNORp(); + double WdecNORn = m_tech_param_ptr->get_WdecNORn(); + total_cap = m_num_in_2nd * m_tech_param_ptr->calc_draincap(WdecNORn, TechParameter::NCH, 1) + m_tech_param_ptr->calc_draincap(WdecNORp, TechParameter::PCH, m_num_in_2nd); + + // part 2: output inverter + // WHS: 20 should go to PARM + double Wdecinvp = m_tech_param_ptr->get_Wdecinvp(); + double Wdecinvn = m_tech_param_ptr->get_Wdecinvn(); + total_cap += m_tech_param_ptr->calc_draincap(Wdecinvn, TechParameter::NCH, 1) + m_tech_param_ptr->calc_draincap(Wdecinvp, TechParameter::PCH, 1) + m_tech_param_ptr->calc_gatecap(Wdecinvn + Wdecinvp, 20); + + return total_cap; +} + +double DecoderUnit::calc_chgaddr_cap() +{ + double total_cap; + + // stage 1: input driver + double Wdecdrivep = m_tech_param_ptr->get_Wdecdrivep(); + double Wdecdriven = m_tech_param_ptr->get_Wdecdriven(); + total_cap = m_tech_param_ptr->calc_draincap(Wdecdrivep, TechParameter::PCH, 1) + m_tech_param_ptr->calc_draincap(Wdecdriven, TechParameter::NCH, 1) + m_tech_param_ptr->calc_gatecap(Wdecdriven, 1); + + /* inverter to produce complement addr, this needs 1/2 */ + /* WHS: assume Wdecinv(np) for this inverter */ + double Wdecinvp = m_tech_param_ptr->get_Wdecinvp(); + double Wdecinvn = m_tech_param_ptr->get_Wdecinvn(); + total_cap += (m_tech_param_ptr->calc_draincap(Wdecinvp, TechParameter::PCH, 1) + m_tech_param_ptr->calc_draincap(Wdecinvn, TechParameter::NCH, 1) + m_tech_param_ptr->calc_gatecap(Wdecinvp, 1) + m_tech_param_ptr->calc_gatecap(Wdecinvn, 1)) / 2; + + /* stage 2: gate cap of level-1 decoder */ + /* WHS: 10 should go to PARM */ + double Wdec3to8p = m_tech_param_ptr->get_Wdec3to8p(); + double Wdec3to8n = m_tech_param_ptr->get_Wdec3to8n(); + total_cap += m_num_out_0th*m_tech_param_ptr->calc_gatecap( Wdec3to8n + Wdec3to8p, 10 ); + + return total_cap; +} + diff --git a/src/mem/ruby/network/orion/Buffer/DecoderUnit.hh b/src/mem/ruby/network/orion/Buffer/DecoderUnit.hh new file mode 100644 index 000000000..93bee26ae --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/DecoderUnit.hh @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2009 Princeton University, and + * Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Hangsheng Wang (Orion 1.0, Princeton) + * Xinping Zhu (Orion 1.0, Princeton) + * Xuning Chen (Orion 1.0, Princeton) + * Bin Li (Orion 2.0, Princeton) + * Kambiz Samadi (Orion 2.0, UC San Diego) + */ + +#ifndef __DECODERUNIT_H__ +#define __DECODERUNIT_H__ + +#include "mem/ruby/network/orion/Type.hh" +#include "mem/ruby/network/orion/TechParameter.hh" + +class DecoderUnit +{ + public: + enum DecModel + { + NO_MODEL = 0, + GENERIC_DEC + }; + + public: + DecoderUnit( + const string& dec_model_str_, + uint32_t dec_width_, + const TechParameter* tech_param_ptr_ + ); + ~DecoderUnit(); + + public: + uint32_t get_dec_width() const { return m_dec_width; } + uint32_t get_num_in_2nd() const { return m_num_in_2nd; } + double get_e_chg_addr() const { return m_e_chg_addr; } + double get_e_chg_output() const { return m_e_chg_output; } + double get_e_chg_l1() const { return m_e_chg_l1; } + + private: + void init(); + double calc_chgl1_cap(); + double calc_select_cap(); + double calc_chgaddr_cap(); + + private: + DecModel m_dec_model; + uint32_t m_dec_width; + const TechParameter* m_tech_param_ptr; + + uint32_t m_num_in_1st; + uint32_t m_num_in_2nd; + uint32_t m_num_out_0th; + uint32_t m_num_out_1st; + + double m_e_chg_l1; + double m_e_chg_output; + double m_e_chg_addr; +}; + +#endif + diff --git a/src/mem/ruby/network/orion/Buffer/MemUnit.cc b/src/mem/ruby/network/orion/Buffer/MemUnit.cc new file mode 100644 index 000000000..159bd87fc --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/MemUnit.cc @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2009 Princeton University, and + * Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Hangsheng Wang (Orion 1.0, Princeton) + * Xinping Zhu (Orion 1.0, Princeton) + * Xuning Chen (Orion 1.0, Princeton) + * Bin Li (Orion 2.0, Princeton) + * Kambiz Samadi (Orion 2.0, UC San Diego) + */ + +#include <iostream> + +#include "mem/ruby/network/orion/Buffer/MemUnit.hh" +#include "mem/ruby/network/orion/Buffer/SRAM.hh" +#include "mem/ruby/network/orion/TechParameter.hh" + +using namespace std; + +MemUnit::MemUnit( + const string& mem_model_str_, + const SRAM* sram_ptr_, + const TechParameter* tech_param_ptr_ + ) +{ + if (mem_model_str_.compare("NORMAL_MEM") == 0) + { + m_mem_model = NORMAL_MEM; + } + else + { + m_mem_model = NO_MODEL; + } + + if (m_mem_model != NO_MODEL) + { + m_sram_ptr = sram_ptr_; + m_tech_param_ptr = tech_param_ptr_; + + init(); + } +} + +MemUnit::~MemUnit() +{} + +void MemUnit::init() +{ + double e_factor = m_tech_param_ptr->get_EnergyFactor(); + + m_e_switch = calc_mem_cap() * e_factor; + + m_i_static = calc_i_static(); +} + +double MemUnit::calc_mem_cap() +{ + double Wmemcella = m_tech_param_ptr->get_Wmemcella(); + double Wmemcellbscale = m_tech_param_ptr->get_Wmemcellbscale(); + double Wmemcellr = m_tech_param_ptr->get_Wmemcellr(); + double Wmemcellw = m_tech_param_ptr->get_Wmemcellw(); + uint32_t num_data_end = m_sram_ptr->get_num_data_end(); + uint32_t num_read_port = m_sram_ptr->get_num_read_port(); + uint32_t num_write_port = m_sram_ptr->get_num_write_port(); + + const TechParameter* tp = m_tech_param_ptr; + + double total_cap = 0; + // part 1: drain capacitance of pass transistors + total_cap += tp->calc_draincap(Wmemcellr, TechParameter::NCH, 1)*num_read_port*num_data_end/2.0; + total_cap += tp->calc_draincap(Wmemcellw, TechParameter::NCH, 1)*num_write_port; + + // has coefficient (1/2 * 2) + // part 2: drain capacitance of memory cell + total_cap += tp->calc_draincap(Wmemcella, TechParameter::NCH, 1) + tp->calc_draincap(Wmemcella*Wmemcellbscale, TechParameter::PCH, 1 + ); + + // has coefficient (1/2 * 2) + // part 3: gate capacitance of memory cell + total_cap += tp->calc_gatecap(Wmemcella, 1) + tp->calc_gatecap(Wmemcella*Wmemcellbscale, 1); + + return total_cap; +} + +double MemUnit::calc_i_static() +{ + double Wmemcella = m_tech_param_ptr->get_Wmemcella(); + double Wmemcellbscale = m_tech_param_ptr->get_Wmemcellbscale(); + double Wmemcellr = m_tech_param_ptr->get_Wmemcellr(); + double Wmemcellw = m_tech_param_ptr->get_Wmemcellw(); + uint32_t num_data_end = m_sram_ptr->get_num_data_end(); + uint32_t num_read_port = m_sram_ptr->get_num_read_port(); + uint32_t num_write_port = m_sram_ptr->get_num_write_port(); + + const TechParameter* tp = m_tech_param_ptr; + + double ret = 0; + // memory cell + //FIXME - why + ret += (Wmemcella*tp->get_NMOS_TAB(0) + Wmemcella*Wmemcellbscale*tp->get_PMOS_TAB(0))*2; + // read port pass tx + ret += (Wmemcellr*tp->get_NMOS_TAB(0)*num_data_end*num_read_port); + // write port pass tx + ret += (Wmemcellw*tp->get_NMOS_TAB(0)*2*num_write_port); + + return ret; +} + diff --git a/src/mem/ruby/network/orion/Buffer/MemUnit.hh b/src/mem/ruby/network/orion/Buffer/MemUnit.hh new file mode 100644 index 000000000..e2858437e --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/MemUnit.hh @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2009 Princeton University, and + * Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Hangsheng Wang (Orion 1.0, Princeton) + * Xinping Zhu (Orion 1.0, Princeton) + * Xuning Chen (Orion 1.0, Princeton) + * Bin Li (Orion 2.0, Princeton) + * Kambiz Samadi (Orion 2.0, UC San Diego) + */ + +#ifndef __MEMUNIT_H__ +#define __MEMUNIT_H__ + +#include "mem/ruby/network/orion/Type.hh" + +class SRAM; +class TechParameter; + +class MemUnit +{ + public: + enum MemModel + { + NO_MODEL = 0, + NORMAL_MEM + }; + + public: + MemUnit( + const string& mem_model_str_, + const SRAM* sram_ptr_, + const TechParameter* tech_param_ptr_ + ); + ~MemUnit(); + + public: + double get_e_switch() const { return m_e_switch; } + double get_i_static() const { return m_i_static; } + + private: + void init(); + double calc_mem_cap(); + double calc_i_static(); + + private: + MemModel m_mem_model; + const SRAM* m_sram_ptr; + const TechParameter* m_tech_param_ptr; + + double m_e_switch; + double m_i_static; +}; + +#endif + diff --git a/src/mem/ruby/network/orion/Buffer/OutdrvUnit.cc b/src/mem/ruby/network/orion/Buffer/OutdrvUnit.cc new file mode 100644 index 000000000..716fc18ee --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/OutdrvUnit.cc @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2009 Princeton University, and + * Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Hangsheng Wang (Orion 1.0, Princeton) + * Xinping Zhu (Orion 1.0, Princeton) + * Xuning Chen (Orion 1.0, Princeton) + * Bin Li (Orion 2.0, Princeton) + * Kambiz Samadi (Orion 2.0, UC San Diego) + */ + +#include "mem/ruby/network/orion/Buffer/OutdrvUnit.hh" +#include "mem/ruby/network/orion/TechParameter.hh" +#include "mem/ruby/network/orion/Buffer/SRAM.hh" + +OutdrvUnit::OutdrvUnit( + const string& outdrv_model_str_, + const SRAM* sram_ptr_, + const TechParameter* tech_param_ptr_ + ) +{ + if (outdrv_model_str_ == string("CACHE_OUTDRV")) + { + m_outdrv_model = CACHE_OUTDRV; + } + else if (outdrv_model_str_ == string("REG_OUTDRV")) + { + m_outdrv_model = REG_OUTDRV; + } + else + { + m_outdrv_model = NO_MODEL; + } + + if (m_outdrv_model != NO_MODEL) + { + m_sram_ptr = sram_ptr_; + m_tech_param_ptr = tech_param_ptr_; + init(); + } + else + { + m_e_select = 0; + m_e_out_1 = 0; + m_e_out_0 = 0; + m_e_chg_data = 0; + } +} + +OutdrvUnit::~OutdrvUnit() +{} + +void OutdrvUnit::init() +{ + double e_factor = m_tech_param_ptr->get_EnergyFactor(); + + m_e_select = calc_select_cap() * e_factor; + m_e_out_1 = calc_outdata_cap(1) * e_factor; + m_e_out_0 = calc_outdata_cap(0) * e_factor; + + switch(m_outdrv_model) + { + case CACHE_OUTDRV: + m_e_chg_data = calc_chgdata_cap() * e_factor; + break; + case REG_OUTDRV: + m_e_chg_data = 0; + break; + default: + printf("error\n"); + } + + m_i_static = calc_i_static(); + return; +} + +double OutdrvUnit::calc_select_cap() +{ + double total_cap; + + // stage 1: inverter + double Woutdrvseln = m_tech_param_ptr->get_Woutdrvseln(); + double Woutdrvselp = m_tech_param_ptr->get_Woutdrvselp(); + total_cap = m_tech_param_ptr->calc_gatecap(Woutdrvseln, 1) + m_tech_param_ptr->calc_gatecap(Woutdrvselp, 1) + m_tech_param_ptr->calc_draincap(Woutdrvseln, TechParameter::NCH, 1) + m_tech_param_ptr->calc_draincap(Woutdrvselp, TechParameter::PCH, 1); + + // stage 2: gate cap of nand gate and nor gate + // only consider 1 gate cap because another and drain cap switch depends on data value + uint32_t line_width = m_sram_ptr->get_line_width(); + double Woutdrvnandn = m_tech_param_ptr->get_Woutdrvnandn(); + double Woutdrvnandp = m_tech_param_ptr->get_Woutdrvnandp(); + double Woutdrvnorn = m_tech_param_ptr->get_Woutdrvnorn(); + double Woutdrvnorp = m_tech_param_ptr->get_Woutdrvnorp(); + total_cap += line_width * (m_tech_param_ptr->calc_gatecap(Woutdrvnandn, 1) + m_tech_param_ptr->calc_gatecap(Woutdrvnandp, 1) + m_tech_param_ptr->calc_gatecap(Woutdrvnorn, 1) + m_tech_param_ptr->calc_gatecap(Woutdrvnorp, 1)); + return total_cap; +} + +double OutdrvUnit::calc_chgdata_cap() +{ + double total_cap; + double Woutdrvnandn = m_tech_param_ptr->get_Woutdrvnandn(); + double Woutdrvnandp = m_tech_param_ptr->get_Woutdrvnandp(); + double Woutdrvnorn = m_tech_param_ptr->get_Woutdrvnorn(); + double Woutdrvnorp = m_tech_param_ptr->get_Woutdrvnorp(); + + total_cap = (m_tech_param_ptr->calc_gatecap(Woutdrvnandn, 1) + m_tech_param_ptr->calc_gatecap(Woutdrvnandp, 1) + m_tech_param_ptr->calc_gatecap(Woutdrvnorn, 1) + m_tech_param_ptr->calc_gatecap(Woutdrvnorp, 1)) / 2.0; + return total_cap; +} + +double OutdrvUnit::calc_outdata_cap(bool value_) +{ + double total_cap = 0; + + // stage 1: drain cap of nand gate or nor gate + if (value_) + { + //drain cap of nand gate + double Woutdrvnandn = m_tech_param_ptr->get_Woutdrvnandn(); + double Woutdrvnandp = m_tech_param_ptr->get_Woutdrvnandp(); + total_cap = m_tech_param_ptr->calc_draincap(Woutdrvnandn, TechParameter::NCH, 2) + 2 * m_tech_param_ptr->calc_draincap(Woutdrvnandp, TechParameter::PCH, 1); + } + else + { + //drain cap of nor gate + double Woutdrvnorn = m_tech_param_ptr->get_Woutdrvnorn(); + double Woutdrvnorp = m_tech_param_ptr->get_Woutdrvnorp(); + total_cap = 2 * m_tech_param_ptr->calc_draincap(Woutdrvnorn, TechParameter::NCH, 1) + m_tech_param_ptr->calc_draincap(Woutdrvnorp, TechParameter::PCH, 2); + } + + // stage 2: gate cap of output inverter + if (value_) + { + double Woutdriverp = m_tech_param_ptr->get_Woutdriverp(); + total_cap += m_tech_param_ptr->calc_gatecap(Woutdriverp, 1); + } + else + { + double Woutdrivern = m_tech_param_ptr->get_Woutdrivern(); + total_cap += m_tech_param_ptr->calc_gatecap(Woutdrivern, 1); + } + + //drian cap of output inverter should be included into bus cap + //TODO + return total_cap; +} + +double OutdrvUnit::calc_i_static() +{ + //FIXME - add static power + return 0; +} + diff --git a/src/mem/ruby/network/orion/Buffer/OutdrvUnit.hh b/src/mem/ruby/network/orion/Buffer/OutdrvUnit.hh new file mode 100644 index 000000000..5d01e2c8a --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/OutdrvUnit.hh @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2009 Princeton University, and + * Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Hangsheng Wang (Orion 1.0, Princeton) + * Xinping Zhu (Orion 1.0, Princeton) + * Xuning Chen (Orion 1.0, Princeton) + * Bin Li (Orion 2.0, Princeton) + * Kambiz Samadi (Orion 2.0, UC San Diego) + */ + +#ifndef __OUTDRVUNIT_H__ +#define __OUTDRVUNIT_H__ + +#include "mem/ruby/network/orion/Type.hh" + +class SRAM; +class TechParameter; + +class OutdrvUnit +{ + public: + enum OutdrvModel + { + NO_MODEL = 0, + CACHE_OUTDRV, + REG_OUTDRV + }; + + public: + OutdrvUnit( + const string& outdrv_model_str_, + const SRAM* sram_ptr_, + const TechParameter* tech_param_ptr_ + ); + ~OutdrvUnit(); + + public: + double get_e_select() const { return m_e_select; } + double get_e_chg_data() const { return m_e_chg_data; } + double get_e_out_0() const { return m_e_out_0; } + double get_e_out_1() const { return m_e_out_1; } + + private: + void init(); + double calc_select_cap(); + double calc_chgdata_cap(); + double calc_outdata_cap(bool value_); + double calc_i_static(); + + private: + OutdrvModel m_outdrv_model; + const SRAM* m_sram_ptr; + const TechParameter* m_tech_param_ptr; + + double m_e_select; + double m_e_out_1; + double m_e_out_0; + double m_e_chg_data; + + double m_i_static; +}; + +#endif + diff --git a/src/mem/ruby/network/orion/Buffer/PrechargeUnit.cc b/src/mem/ruby/network/orion/Buffer/PrechargeUnit.cc new file mode 100644 index 000000000..ac91edb43 --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/PrechargeUnit.cc @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2009 Princeton University, and + * Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Hangsheng Wang (Orion 1.0, Princeton) + * Xinping Zhu (Orion 1.0, Princeton) + * Xuning Chen (Orion 1.0, Princeton) + * Bin Li (Orion 2.0, Princeton) + * Kambiz Samadi (Orion 2.0, UC San Diego) + */ + +#include "mem/ruby/network/orion/Buffer/PrechargeUnit.hh" +#include "mem/ruby/network/orion/TechParameter.hh" +#include "mem/ruby/network/orion/Buffer/SRAM.hh" + +PrechargeUnit::PrechargeUnit( + const string& pre_model_str_, + double pre_load_, + const SRAM* sram_ptr_, + const TechParameter* tech_param_ptr_ + ) +{ + if (pre_model_str_ == "SINGLE_BITLINE") + { + m_pre_model = SINGLE_BITLINE; + } + else if (pre_model_str_ == "EQU_BITLINE") + { + m_pre_model = EQU_BITLINE; + } + else if (pre_model_str_ == "SINGLE_OTHER") + { + m_pre_model = SINGLE_OTHER; + } + else + { + m_pre_model = NO_MODEL; + } + + if (m_pre_model != NO_MODEL) + { + m_pre_load = pre_load_; + m_sram_ptr = sram_ptr_; + m_tech_param_ptr = tech_param_ptr_; + + init(); + } +} + +PrechargeUnit::~PrechargeUnit() +{ +} + +void PrechargeUnit::init() +{ + double period = m_tech_param_ptr->get_period(); + m_pre_size = m_tech_param_ptr->calc_driver_psize(m_pre_load, period/8.0); + //FIXME - shouldn't be added + double Wdecinvn = m_tech_param_ptr->get_Wdecinvn(); + double Wdecinvp = m_tech_param_ptr->get_Wdecinvp(); + m_pre_size += m_pre_size*Wdecinvn/Wdecinvp; + + uint32_t num_gate = calc_num_pre_gate(); + + // WHS: 10 should go to PARM + double e_factor = m_tech_param_ptr->get_EnergyFactor(); + m_e_charge_gate = calc_pre_cap(m_pre_size, 10) * num_gate * e_factor; + + uint32_t num_data_end = m_sram_ptr->get_num_data_end(); + if (num_data_end == 2) + { + e_factor = m_tech_param_ptr->get_SenseEnergyFactor(); + } + else + { + e_factor = m_tech_param_ptr->get_EnergyFactor(); + } + uint32_t num_drain = calc_num_pre_drain(); + m_e_charge_drain = m_tech_param_ptr->calc_draincap(m_pre_size, TechParameter::PCH, 1)*num_drain*e_factor; + + // static power + double PMOS_TAB_0 = m_tech_param_ptr->get_PMOS_TAB(0); + m_i_static = num_gate*m_pre_size*PMOS_TAB_0; +} + +uint32_t PrechargeUnit::calc_num_pre_gate() +{ + switch(m_pre_model) + { + case SINGLE_BITLINE: return 2; + case EQU_BITLINE: return 3; + case SINGLE_OTHER: return 1; + default: printf("error\n"); return 0; + } +} + +uint32_t PrechargeUnit::calc_num_pre_drain() +{ + switch(m_pre_model) + { + case SINGLE_BITLINE: return 1; + case EQU_BITLINE: return 2; + case SINGLE_OTHER: return 1; + default: printf("error\n"); return 0; + } +} + +double PrechargeUnit::calc_pre_cap(double width_, double length_) +{ + return m_tech_param_ptr->calc_gatecap(width_, length_); +} + diff --git a/src/mem/ruby/network/orion/Buffer/PrechargeUnit.hh b/src/mem/ruby/network/orion/Buffer/PrechargeUnit.hh new file mode 100644 index 000000000..e6f56eb3a --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/PrechargeUnit.hh @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2009 Princeton University, and + * Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Hangsheng Wang (Orion 1.0, Princeton) + * Xinping Zhu (Orion 1.0, Princeton) + * Xuning Chen (Orion 1.0, Princeton) + * Bin Li (Orion 2.0, Princeton) + * Kambiz Samadi (Orion 2.0, UC San Diego) + */ + +#ifndef __PRECHARGEUNIT_H__ +#define __PRECHARGEUNIT_H__ + +#include "mem/ruby/network/orion/Type.hh" + +class SRAM; +class TechParameter; + +class PrechargeUnit +{ + public: + enum PrechargeModel + { + NO_MODEL = 0, + SINGLE_BITLINE, + EQU_BITLINE, + SINGLE_OTHER + }; + + public: + PrechargeUnit( + const string& pre_model_str_, + double pre_load_, + const SRAM* sram_ptr_, + const TechParameter* tech_param_ptr_ + ); + ~PrechargeUnit(); + + public: + double get_e_charge_gate() const { return m_e_charge_gate; } + double get_e_charge_drain() const { return m_e_charge_drain; } + double get_i_static() const { return m_i_static; } + + private: + void init(); + uint32_t calc_num_pre_gate(); + uint32_t calc_num_pre_drain(); + double calc_pre_cap(double width_, double length_); + + private: + PrechargeModel m_pre_model; + double m_pre_load; + const SRAM* m_sram_ptr; + const TechParameter* m_tech_param_ptr; + + double m_pre_size; + + double m_e_charge_gate; + double m_e_charge_drain; + + double m_i_static; +}; + +#endif + diff --git a/src/mem/ruby/network/orion/Buffer/Register.cc b/src/mem/ruby/network/orion/Buffer/Register.cc new file mode 100644 index 000000000..364e5a833 --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/Register.cc @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2009 Princeton University, and + * Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Hangsheng Wang (Orion 1.0, Princeton) + * Xinping Zhu (Orion 1.0, Princeton) + * Xuning Chen (Orion 1.0, Princeton) + * Bin Li (Orion 2.0, Princeton) + * Kambiz Samadi (Orion 2.0, UC San Diego) + */ + +#include <iostream> +#include <cassert> + +#include "mem/ruby/network/orion/Buffer/Register.hh" +#include "mem/ruby/network/orion/TechParameter.hh" +#include "mem/ruby/network/orion/FlipFlop.hh" + +using namespace std; + +Register::Register( + uint32_t num_entry_, + uint32_t line_width_, + const TechParameter *tech_param_ptr_ + ) +{ + assert(num_entry_ == num_entry_); + assert(line_width_ == line_width_); + + m_num_entry = num_entry_; + m_line_width = line_width_; + m_tech_param_ptr = tech_param_ptr_; + + init(); +} + +Register::~Register() +{ + delete m_ff_ptr; +} + +double Register::calc_e_read() const +{ + // average read energy for one buffer entry + double e_read = 0; + + + // for each read operation, the energy consists of one read operation and n write + // operateion. n means there is n flits in the buffer before read operation. + // assume n is info->n_entry * 0.25. + // + if (m_num_entry > 1) + { + e_read = (m_avg_read + m_num_entry*0.25*m_avg_write); + } + else + { + e_read = m_avg_read; + } + return e_read; +} + +double Register::calc_e_write() const +{ + // average write energy for one buffer entry + double e_write = 0; + + e_write = m_avg_write; + return e_write; +} + +double Register::calc_i_static() const +{ + double i_static = m_ff_ptr->get_i_static()*m_line_width*m_num_entry; + + return i_static; +} + +void Register::init() +{ + m_ff_ptr = new FlipFlop("NEG_DFF", 0, m_tech_param_ptr); + + uint32_t num_clock = m_line_width; + m_avg_read = m_ff_ptr->get_e_clock()*((double)num_clock)/2.0; + + double num_switch = m_line_width/2.0; + m_avg_write = m_ff_ptr->get_e_switch()*num_switch+m_ff_ptr->get_e_clock()*num_clock; + return; +} diff --git a/src/mem/ruby/network/orion/Buffer/Register.hh b/src/mem/ruby/network/orion/Buffer/Register.hh new file mode 100644 index 000000000..30e8b80f3 --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/Register.hh @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2009 Princeton University, and + * Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Hangsheng Wang (Orion 1.0, Princeton) + * Xinping Zhu (Orion 1.0, Princeton) + * Xuning Chen (Orion 1.0, Princeton) + * Bin Li (Orion 2.0, Princeton) + * Kambiz Samadi (Orion 2.0, UC San Diego) + */ + +#ifndef __REGISTER_H__ +#define __REGISTER_H__ + +#include "mem/ruby/network/orion/Type.hh" + +class TechParameter; +class FlipFlop; + +class Register +{ + public: + Register( + uint32_t num_entry_, + uint32_t line_width_, + const TechParameter* tech_param_ptr_ + ); + ~Register(); + + public: + double calc_e_read() const; + double calc_e_write() const; + double calc_i_static() const; + + private: + void init(); + + private: + uint32_t m_num_entry; + uint32_t m_line_width; + const TechParameter* m_tech_param_ptr; + + FlipFlop* m_ff_ptr; + + double m_avg_read; + double m_avg_write; +}; + +#endif diff --git a/src/mem/ruby/network/orion/Buffer/SConscript b/src/mem/ruby/network/orion/Buffer/SConscript new file mode 100644 index 000000000..3db8c4a01 --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/SConscript @@ -0,0 +1,43 @@ +# Copyright (c) 2010 Massachusetts Institute of Technology +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Tushar Krishna + +Import('*') + +if not env['RUBY']: + Return() + +Source('AmpUnit.cc') +Source('BitlineUnit.cc') +Source('Buffer.cc') +Source('DecoderUnit.cc') +Source('MemUnit.cc') +Source('OutdrvUnit.cc') +Source('PrechargeUnit.cc') +Source('Register.cc') +Source('SRAM.cc') +Source('WordlineUnit.cc') diff --git a/src/mem/ruby/network/orion/Buffer/SRAM.cc b/src/mem/ruby/network/orion/Buffer/SRAM.cc new file mode 100644 index 000000000..d8f500de5 --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/SRAM.cc @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2009 Princeton University, and + * Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Hangsheng Wang (Orion 1.0, Princeton) + * Xinping Zhu (Orion 1.0, Princeton) + * Xuning Chen (Orion 1.0, Princeton) + * Bin Li (Orion 2.0, Princeton) + * Kambiz Samadi (Orion 2.0, UC San Diego) + */ + +#include <iostream> +#include <cmath> +#include <cassert> + +#include "mem/ruby/network/orion/Buffer/SRAM.hh" +#include "mem/ruby/network/orion/Buffer/OutdrvUnit.hh" +#include "mem/ruby/network/orion/Buffer/AmpUnit.hh" +#include "mem/ruby/network/orion/Buffer/BitlineUnit.hh" +#include "mem/ruby/network/orion/Buffer/MemUnit.hh" +#include "mem/ruby/network/orion/Buffer/PrechargeUnit.hh" +#include "mem/ruby/network/orion/Buffer/WordlineUnit.hh" +#include "mem/ruby/network/orion/Buffer/DecoderUnit.hh" + +using namespace std; + +SRAM::SRAM( + uint32_t num_entry_, + uint32_t line_width_, + bool is_fifo_, + bool is_outdrv_, + uint32_t num_read_port_, + uint32_t num_write_port_, + uint32_t num_data_end_, + const string& rowdec_model_str_, + const string& wl_model_str_, + const string& bl_pre_model_str_, + const string& mem_model_str_, + const string& bl_model_str_, + const string& amp_model_str_, + const string& outdrv_model_str_, + const TechParameter* tech_param_ptr_ + ) +{ + assert(num_entry_ == num_entry_); + assert(line_width_ == line_width_); + assert(num_read_port_ == num_read_port_); + assert(num_write_port_ == num_write_port_); + assert(num_data_end_ == num_data_end_); + + m_num_entry = num_entry_; + m_line_width = line_width_; + m_is_fifo = is_fifo_; + m_is_outdrv = is_outdrv_; + + m_num_read_port = num_read_port_; + m_num_write_port = num_write_port_; + m_num_data_end = num_data_end_; + + m_rowdec_model_str = rowdec_model_str_; + m_wl_model_str = wl_model_str_; + m_bl_pre_model_str = bl_pre_model_str_; + m_mem_model_str = mem_model_str_; + m_bl_model_str = bl_model_str_; + m_amp_model_str = amp_model_str_; + m_outdrv_model_str = outdrv_model_str_; + m_tech_param_ptr = tech_param_ptr_; + + init(); +} + +SRAM::~SRAM() +{ + delete m_outdrv_unit_ptr; + delete m_amp_unit_ptr; + delete m_bl_unit_ptr; + delete m_mem_unit_ptr; + delete m_bl_pre_unit_ptr; + delete m_wl_unit_ptr; + delete m_rowdec_unit_ptr; +} + +double SRAM::calc_e_read( + bool is_max_ + ) const +{ + double e_atomic; + double e_read = 0; + + // decoder + if (m_rowdec_unit_ptr != NULL) + { + e_atomic = m_rowdec_unit_ptr->get_e_chg_addr()*m_rowdec_unit_ptr->get_dec_width()*(is_max_? 1:0.5); + e_atomic += m_rowdec_unit_ptr->get_e_chg_output(); + // assume all 1st-level decoders change output + e_atomic += m_rowdec_unit_ptr->get_e_chg_l1()*m_rowdec_unit_ptr->get_num_in_2nd(); + e_read += e_atomic; + } + + //wordline + e_atomic = m_wl_unit_ptr->get_e_read(); + e_read += e_atomic; + + //bitline pre + e_atomic = m_bl_pre_unit_ptr->get_e_charge_gate()*m_line_width; + if (m_num_data_end == 2) + { + e_atomic += m_bl_pre_unit_ptr->get_e_charge_drain()*m_line_width; + } + else + { + e_atomic += m_bl_pre_unit_ptr->get_e_charge_drain()*m_line_width*(is_max_? 1:0.5); + } + e_read += e_atomic; + + //bitline + if (m_num_data_end == 2) + { + e_atomic = m_bl_unit_ptr->get_e_col_read()*m_line_width; + } + else + { + e_atomic = m_bl_unit_ptr->get_e_col_read()*m_line_width*(is_max_? 1:0.5); + } + e_read += e_atomic; + + if (m_num_data_end == 2) + { + e_atomic = m_amp_unit_ptr->get_e_access()*m_line_width; + e_read += e_atomic; + } + + if (m_outdrv_unit_ptr != NULL) + { + e_atomic = m_outdrv_unit_ptr->get_e_select(); + + e_atomic += m_outdrv_unit_ptr->get_e_chg_data()*m_line_width*(is_max_? 1:0.5); + + //assume 1 and 0 are uniformly distributed + if ((m_outdrv_unit_ptr->get_e_out_1() >= m_outdrv_unit_ptr->get_e_out_0()) || (!is_max_)) + { + e_atomic += m_outdrv_unit_ptr->get_e_out_1()*m_line_width*(is_max_? 1:0.5); + } + if ((m_outdrv_unit_ptr->get_e_out_1() < m_outdrv_unit_ptr->get_e_out_0()) || (!is_max_)) + { + e_atomic += m_outdrv_unit_ptr->get_e_out_0()*m_line_width*(is_max_? 1:0.5); + } + + e_read += e_atomic; + } + + return e_read; +} + +double SRAM::calc_e_write( + bool is_max_ + ) const +{ + double e_atomic; + double e_write = 0; + + // decoder + if (m_rowdec_unit_ptr != NULL) + { + e_atomic = m_rowdec_unit_ptr->get_e_chg_addr()*m_rowdec_unit_ptr->get_dec_width()*(is_max_? 1:0.5); + e_atomic += m_rowdec_unit_ptr->get_e_chg_output(); + // assume all 1st-level decoders change output + e_atomic += m_rowdec_unit_ptr->get_e_chg_l1()*m_rowdec_unit_ptr->get_num_in_2nd(); + e_write += e_atomic; + } + + //wordline + e_atomic = m_wl_unit_ptr->get_e_write(); + e_write += e_atomic; + + //bitline + e_atomic = m_bl_unit_ptr->get_e_col_wrtie()*m_line_width*(is_max_? 1:0.5); + e_write += e_atomic; + + //mem cell + e_atomic = m_mem_unit_ptr->get_e_switch()*m_line_width*(is_max_? 1:0.5); + e_write += e_atomic; + + return e_write; +} + +double SRAM::calc_i_static() const +{ + double i_static = 0; + + i_static += m_bl_unit_ptr->get_i_static()*m_line_width*m_num_write_port; + i_static += m_mem_unit_ptr->get_i_static()*m_num_entry*m_line_width; + i_static += m_bl_pre_unit_ptr->get_i_static()*m_line_width*m_num_read_port; + i_static += m_wl_unit_ptr->get_i_static()*m_num_entry*(m_num_read_port+m_num_write_port); + + return i_static; +} + +void SRAM::init() +{ + // output driver unit + if (m_is_outdrv) + { + m_outdrv_unit_ptr = new OutdrvUnit(m_outdrv_model_str, this, m_tech_param_ptr); + } + else + { + m_outdrv_unit_ptr = NULL; + } + + // sense amplifier unit + if (m_num_data_end == 2) + { + m_amp_unit_ptr = new AmpUnit(m_amp_model_str, m_tech_param_ptr); + } + else + { + m_amp_unit_ptr = NULL; + } + + // bitline unit + m_bl_unit_ptr = new BitlineUnit(m_bl_model_str, this, m_tech_param_ptr); + + // mem unit + m_mem_unit_ptr = new MemUnit(m_mem_model_str, this, m_tech_param_ptr); + + // precharge unit + double bl_pre_unit_load = m_bl_unit_ptr->get_pre_unit_load(); + m_bl_pre_unit_ptr = new PrechargeUnit(m_bl_pre_model_str, bl_pre_unit_load, this, m_tech_param_ptr); + + // wordline unit + m_wl_unit_ptr = new WordlineUnit(m_wl_model_str, this, m_tech_param_ptr); + + // decode unit + if (!m_is_fifo) + { + m_rowdec_width = (uint32_t)log2((double)m_num_entry); + m_rowdec_unit_ptr = new DecoderUnit(m_rowdec_model_str, m_rowdec_width, m_tech_param_ptr); + } + else + { + m_rowdec_unit_ptr = NULL; + } + return; +} + + diff --git a/src/mem/ruby/network/orion/Buffer/SRAM.hh b/src/mem/ruby/network/orion/Buffer/SRAM.hh new file mode 100644 index 000000000..7b3f46698 --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/SRAM.hh @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2009 Princeton University, and + * Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Hangsheng Wang (Orion 1.0, Princeton) + * Xinping Zhu (Orion 1.0, Princeton) + * Xuning Chen (Orion 1.0, Princeton) + * Bin Li (Orion 2.0, Princeton) + * Kambiz Samadi (Orion 2.0, UC San Diego) + */ + +#ifndef __SRAM_H__ +#define __SRAM_H__ + +#include "mem/ruby/network/orion/Type.hh" +#include "mem/ruby/network/orion/OrionConfig.hh" +#include "mem/ruby/network/orion/TechParameter.hh" + +class OutdrvUnit; +class AmpUnit; +class BitlineUnit; +class MemUnit; +class PrechargeUnit; +class WordlineUnit; +class DecoderUnit; + +class SRAM +{ + public: + SRAM( + uint32_t num_entry_, + uint32_t line_width_, + bool is_fifo_, + bool is_outdrv_, + uint32_t num_read_port_, + uint32_t num_write_port_, + uint32_t num_data_end_, + const string& rowdec_model_str_, + const string& wl_model_str_, + const string& bl_pre_model_str_, + const string& mem_model_str_, + const string& bl_model_str_, + const string& amp_model_str_, + const string& outdrv_model_str_, + const TechParameter* tech_param_ptr_ + ); + ~SRAM(); + + public: + uint32_t get_line_width() const { return m_line_width; } + uint32_t get_num_data_end() const { return m_num_data_end; } + uint32_t get_num_read_port() const { return m_num_read_port; } + uint32_t get_num_write_port() const { return m_num_write_port; } + uint32_t get_num_port() const { return (m_num_read_port+m_num_write_port); } + bool get_is_outdrv() const { return m_is_outdrv; } + uint32_t get_num_row() const { return m_num_entry; } + uint32_t get_num_col() const { return m_line_width; } + + double calc_e_read(bool is_max_) const; + double calc_e_write(bool is_max_) const; + double calc_i_static() const; + + private: + void init(); + + private: + uint32_t m_num_entry; + uint32_t m_line_width; + bool m_is_fifo; + bool m_is_outdrv; + string m_rowdec_model_str; + string m_wl_model_str; + string m_bl_pre_model_str; + string m_mem_model_str; + string m_bl_model_str; + string m_amp_model_str; + string m_outdrv_model_str; + const TechParameter* m_tech_param_ptr; + + OutdrvUnit* m_outdrv_unit_ptr; + AmpUnit* m_amp_unit_ptr; + BitlineUnit* m_bl_unit_ptr; + MemUnit* m_mem_unit_ptr; + PrechargeUnit* m_bl_pre_unit_ptr; + WordlineUnit* m_wl_unit_ptr; + DecoderUnit* m_rowdec_unit_ptr; + + uint32_t m_num_read_port; + uint32_t m_num_write_port; + uint32_t m_num_data_end; + + uint32_t m_rowdec_width; +}; + +#endif + diff --git a/src/mem/ruby/network/orion/Buffer/WordlineUnit.cc b/src/mem/ruby/network/orion/Buffer/WordlineUnit.cc new file mode 100644 index 000000000..bc28444e2 --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/WordlineUnit.cc @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2009 Princeton University, and + * Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Hangsheng Wang (Orion 1.0, Princeton) + * Xinping Zhu (Orion 1.0, Princeton) + * Xuning Chen (Orion 1.0, Princeton) + * Bin Li (Orion 2.0, Princeton) + * Kambiz Samadi (Orion 2.0, UC San Diego) + */ + +#include "mem/ruby/network/orion/Buffer/WordlineUnit.hh" +#include "mem/ruby/network/orion/Buffer/SRAM.hh" +#include "mem/ruby/network/orion/TechParameter.hh" + +WordlineUnit::WordlineUnit( + const string& wl_model_str_, + const SRAM* sram_ptr_, + const TechParameter* tech_param_ptr_ + ) +{ + if (wl_model_str_ == string("RW_WORDLINE")) + { + m_wl_model = RW_WORDLINE; + } + else if (wl_model_str_ == string("WO_WORDLINE")) + { + m_wl_model = WO_WORDLINE; + } + else + { + m_wl_model = NO_MODEL; + } + + if (m_wl_model != NO_MODEL) + { + m_sram_ptr = sram_ptr_; + m_tech_param_ptr = tech_param_ptr_; + + init(); + } +} + +WordlineUnit::~WordlineUnit() +{} + +void WordlineUnit::init() +{ + uint32_t num_port = m_sram_ptr->get_num_port(); + uint32_t num_read_port = m_sram_ptr->get_num_read_port(); + uint32_t num_col = m_sram_ptr->get_num_col(); + uint32_t num_data_end = m_sram_ptr->get_num_data_end(); + double RegCellWidth = m_tech_param_ptr->get_RegCellWidth(); + double BitlineSpacing = m_tech_param_ptr->get_BitlineSpacing(); + + if (num_data_end == 2) + { + m_wl_len = num_col*(RegCellWidth + 2*num_port*BitlineSpacing); + } + else + { + m_wl_len = num_col*(RegCellWidth + (2*num_port-num_read_port)*BitlineSpacing); + } + + double wl_cmetal; + if (num_port > 1) + { + wl_cmetal = m_tech_param_ptr->get_CC3M3metal(); + } + else + { + wl_cmetal = m_tech_param_ptr->get_CM3metal(); + } + + m_wl_wire_cap = m_wl_len*wl_cmetal; + + double e_factor = m_tech_param_ptr->get_EnergyFactor(); + double Wmemcellr = m_tech_param_ptr->get_Wmemcellr(); + double Wmemcellw = m_tech_param_ptr->get_Wmemcellw(); + double Woutdrivern = m_tech_param_ptr->get_Woutdrivern(); + double Woutdriverp = m_tech_param_ptr->get_Woutdriverp(); + double NMOS_TAB_0 = m_tech_param_ptr->get_NMOS_TAB(0); + double PMOS_TAB_0 = m_tech_param_ptr->get_PMOS_TAB(0); + switch(m_wl_model) + { + case RW_WORDLINE: + m_e_read = calc_wordline_cap(num_col*num_data_end, Wmemcellr) * e_factor; + m_e_write = calc_wordline_cap(num_col*2, Wmemcellw) * e_factor; + m_i_static = (Woutdrivern*NMOS_TAB_0 + Woutdriverp*PMOS_TAB_0); + break; + case WO_WORDLINE: + m_e_read = 0; + m_e_write = calc_wordline_cap(num_col*2, Wmemcellw)*e_factor; + m_i_static = 0; + break; + default: + printf("error\n"); + } + return; +} + +double WordlineUnit::calc_wordline_cap( + uint32_t num_mos_, + double mos_width_ + ) const +{ + double total_cap; + + // part 1: line cap, including gate cap of pass tx's and metal cap + double BitWidth = m_tech_param_ptr->get_BitWidth(); + total_cap = m_tech_param_ptr->calc_gatecappass(mos_width_, BitWidth/2.0-mos_width_)*num_mos_ + m_wl_wire_cap; + + // part 2: input driver + double period = m_tech_param_ptr->get_period(); + double psize, nsize; + psize = m_tech_param_ptr->calc_driver_psize(total_cap, period/16.0); + double Wdecinvn = m_tech_param_ptr->get_Wdecinvn(); + double Wdecinvp = m_tech_param_ptr->get_Wdecinvp(); + nsize = psize*Wdecinvn/Wdecinvp; + + // WHS: 20 should go to PARM + total_cap += m_tech_param_ptr->calc_draincap(nsize, TechParameter::NCH, 1) + m_tech_param_ptr->calc_draincap(psize, TechParameter::PCH, 1) + m_tech_param_ptr->calc_gatecap(psize+nsize, 20); + + return total_cap; +} + diff --git a/src/mem/ruby/network/orion/Buffer/WordlineUnit.hh b/src/mem/ruby/network/orion/Buffer/WordlineUnit.hh new file mode 100644 index 000000000..4083f5dcf --- /dev/null +++ b/src/mem/ruby/network/orion/Buffer/WordlineUnit.hh @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2009 Princeton University, and + * Regents of the University of California + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Hangsheng Wang (Orion 1.0, Princeton) + * Xinping Zhu (Orion 1.0, Princeton) + * Xuning Chen (Orion 1.0, Princeton) + * Bin Li (Orion 2.0, Princeton) + * Kambiz Samadi (Orion 2.0, UC San Diego) + */ + +#ifndef __WORDLINEUNIT_H__ +#define __WORDLINEUNIT_H__ + +#include "mem/ruby/network/orion/Type.hh" + +class SRAM; +class TechParameter; + +class WordlineUnit +{ + public: + enum WordlineModel + { + NO_MODEL = 0, + RW_WORDLINE, + WO_WORDLINE + }; + + public: + WordlineUnit( + const string& wl_model_str_, + const SRAM* sram_ptr_, + const TechParameter* tech_param_ptr_ + ); + ~WordlineUnit(); + + public: + double get_e_read() const { return m_e_read; } + double get_e_write() const { return m_e_write; } + double get_i_static() const { return m_i_static; } + + private: + void init(); + double calc_wordline_cap(uint32_t num_mos_, double mos_width_) const; + double calc_i_static(); + + private: + WordlineModel m_wl_model; + const SRAM* m_sram_ptr; + const TechParameter* m_tech_param_ptr; + + double m_wl_len; + double m_wl_wire_cap; + + double m_e_read; + double m_e_write; + + double m_i_static; +}; + +#endif + |