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author | Nathan Binkert <nate@binkert.org> | 2009-05-11 10:38:43 -0700 |
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committer | Nathan Binkert <nate@binkert.org> | 2009-05-11 10:38:43 -0700 |
commit | 2f30950143cc70bc42a3c8a4111d7cf8198ec881 (patch) | |
tree | 708f6c22edb3c6feb31dd82866c26623a5329580 /src/mem/ruby/network/orion/power_bus.hh | |
parent | c70241810d4e4f523f173c1646b008dc40faad8e (diff) | |
download | gem5-2f30950143cc70bc42a3c8a4111d7cf8198ec881.tar.xz |
ruby: Import ruby and slicc from GEMS
We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
Diffstat (limited to 'src/mem/ruby/network/orion/power_bus.hh')
-rw-r--r-- | src/mem/ruby/network/orion/power_bus.hh | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/src/mem/ruby/network/orion/power_bus.hh b/src/mem/ruby/network/orion/power_bus.hh new file mode 100644 index 000000000..e1c3ef565 --- /dev/null +++ b/src/mem/ruby/network/orion/power_bus.hh @@ -0,0 +1,64 @@ +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _POWER_BUS_H +#define _POWER_BUS_H + +typedef enum { + RESULT_BUS = 1, + GENERIC_BUS, + BUS_MAX_MODEL +} power_bus_model; + +typedef enum { + IDENT_ENC = 1, /* identity encoding */ + TRANS_ENC, /* transition encoding */ + BUSINV_ENC, /* bus inversion encoding */ + BUS_MAX_ENC +} power_bus_enc; + + +typedef struct { + int model; + int encoding; + unsigned data_width; + unsigned grp_width; + unsigned long int n_switch; + double e_switch; + /* redundant field */ + unsigned bit_width; + unsigned long int bus_mask; +} power_bus; + +extern int power_bus_init(power_bus *bus, int model, int encoding, unsigned width, unsigned grp_width, unsigned n_snd, unsigned n_rcv, double length, double time); + +extern int bus_record(power_bus *bus, unsigned long int old_state, unsigned long int new_state); + +extern double bus_report(power_bus *bus); + +#endif |