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authorNilay Vaish <nilay@cs.wisc.edu>2013-02-10 21:43:17 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2013-02-10 21:43:17 -0600
commitcb7782f78d337527d8ea3d593645fc67cca54d23 (patch)
treeac0602477455b2364a32f788b0e1e6bae1fa999b /src/mem/ruby/network/simple/PerfectSwitch.hh
parent253e8edf13c4d7bee6bd13f84fdfa6cf40a0c5c3 (diff)
downloadgem5-cb7782f78d337527d8ea3d593645fc67cca54d23.tar.xz
ruby: enable multiple clock domains
This patch allows ruby to have multiple clock domains. As I understand with this patch, controllers can have different frequencies. The entire network needs to run at a single frequency. The idea is that with in an object, time is treated in terms of cycles. But the messages that are passed from one entity to another should contain the time in Ticks. As of now, this is only true for the message buffers, but not for the links in the network. As I understand the code, all the entities in different networks (simple, garnet-fixed, garnet-flexible) should be clocked at the same frequency. Another problem is that the directory controller has to operate at the same frequency as the ruby system. This is because the memory controller does not make use of the Message Buffer, and instead implements a buffer of its own. So, it has no idea of the frequency at which the directory controller is operating and uses ruby system's frequency for scheduling events.
Diffstat (limited to 'src/mem/ruby/network/simple/PerfectSwitch.hh')
-rw-r--r--src/mem/ruby/network/simple/PerfectSwitch.hh2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.hh b/src/mem/ruby/network/simple/PerfectSwitch.hh
index ffd1f84ba..695c848bc 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.hh
+++ b/src/mem/ruby/network/simple/PerfectSwitch.hh
@@ -63,7 +63,7 @@ class PerfectSwitch : public Consumer
{ return csprintf("PerfectSwitch-%i", m_switch_id); }
void init(SimpleNetwork *);
- void addInPort(const std::vector<MessageBuffer*>& in, Switch *);
+ void addInPort(const std::vector<MessageBuffer*>& in);
void addOutPort(const std::vector<MessageBuffer*>& out,
const NetDest& routing_table_entry);
void clearRoutingTables();