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authorNilay Vaish <nilay@cs.wisc.edu>2012-10-15 17:51:57 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2012-10-15 17:51:57 -0500
commit5ffc16593997b35f4f1abbd149e01169e6bbcff5 (patch)
tree647411a3d027f2bdfaf750f65107affb6d9c002d /src/mem/ruby/network/simple
parent07ce90f7aa28a507493da905ba1881972250bb3a (diff)
downloadgem5-5ffc16593997b35f4f1abbd149e01169e6bbcff5.tar.xz
ruby: improved support for functional accesses
This patch adds support to different entities in the ruby memory system for more reliable functional read/write accesses. Only the simple network has been augmented as of now. Later on Garnet will also support functional accesses. The patch adds functional access code to all the different types of messages that protocols can send around. These messages are functionally accessed by going through the buffers maintained by the network entities. The patch also rectifies some of the bugs found in coherence protocols while testing the patch. With this patch applied, functional writes always succeed. But functional reads can still fail.
Diffstat (limited to 'src/mem/ruby/network/simple')
-rw-r--r--src/mem/ruby/network/simple/PerfectSwitch.cc1
-rw-r--r--src/mem/ruby/network/simple/SimpleNetwork.cc38
-rw-r--r--src/mem/ruby/network/simple/SimpleNetwork.hh3
-rw-r--r--src/mem/ruby/network/simple/Switch.cc22
-rw-r--r--src/mem/ruby/network/simple/Switch.hh3
5 files changed, 66 insertions, 1 deletions
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.cc b/src/mem/ruby/network/simple/PerfectSwitch.cc
index 2c845683d..b38b6d539 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.cc
+++ b/src/mem/ruby/network/simple/PerfectSwitch.cc
@@ -343,4 +343,3 @@ PerfectSwitch::print(std::ostream& out) const
{
out << "[PerfectSwitch " << m_switch_id << "]";
}
-
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc b/src/mem/ruby/network/simple/SimpleNetwork.cc
index 7aa8e62f9..9df9ed3a5 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc
@@ -327,3 +327,41 @@ SimpleNetworkParams::create()
{
return new SimpleNetwork(this);
}
+
+/*
+ * The simple network has an array of switches. These switches have buffers
+ * that need to be accessed for functional reads and writes. Also the links
+ * between different switches have buffers that need to be accessed.
+ */
+bool
+SimpleNetwork::functionalRead(Packet *pkt)
+{
+ for (unsigned int i = 0; i < m_switch_ptr_vector.size(); i++) {
+ if (m_switch_ptr_vector[i]->functionalRead(pkt)) {
+ return true;
+ }
+ }
+
+ for (unsigned int i = 0; i < m_buffers_to_free.size(); ++i) {
+ if (m_buffers_to_free[i]->functionalRead(pkt)) {
+ return true;
+ }
+ }
+
+ return false;
+}
+
+uint32_t
+SimpleNetwork::functionalWrite(Packet *pkt)
+{
+ uint32_t num_functional_writes = 0;
+
+ for (unsigned int i = 0; i < m_switch_ptr_vector.size(); i++) {
+ num_functional_writes += m_switch_ptr_vector[i]->functionalWrite(pkt);
+ }
+
+ for (unsigned int i = 0; i < m_buffers_to_free.size(); ++i) {
+ num_functional_writes += m_buffers_to_free[i]->functionalWrite(pkt);
+ }
+ return num_functional_writes;
+}
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.hh b/src/mem/ruby/network/simple/SimpleNetwork.hh
index 6dfaa2724..879446822 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.hh
+++ b/src/mem/ruby/network/simple/SimpleNetwork.hh
@@ -86,6 +86,9 @@ class SimpleNetwork : public Network
void print(std::ostream& out) const;
+ bool functionalRead(Packet *pkt);
+ uint32_t functionalWrite(Packet *pkt);
+
private:
void checkNetworkAllocation(NodeID id, bool ordered, int network_num);
void addLink(SwitchID src, SwitchID dest, int link_latency);
diff --git a/src/mem/ruby/network/simple/Switch.cc b/src/mem/ruby/network/simple/Switch.cc
index 5c2f5a717..a0a27f758 100644
--- a/src/mem/ruby/network/simple/Switch.cc
+++ b/src/mem/ruby/network/simple/Switch.cc
@@ -217,6 +217,28 @@ Switch::print(std::ostream& out) const
// FIXME printing
out << "[Switch]";
}
+bool
+Switch::functionalRead(Packet *pkt)
+{
+ // Access the buffers in the switch for performing a functional read
+ for (unsigned int i = 0; i < m_buffers_to_free.size(); ++i) {
+ if (m_buffers_to_free[i]->functionalRead(pkt)) {
+ return true;
+ }
+ }
+ return false;
+}
+
+uint32_t
+Switch::functionalWrite(Packet *pkt)
+{
+ // Access the buffers in the switch for performing a functional write
+ uint32_t num_functional_writes = 0;
+ for (unsigned int i = 0; i < m_buffers_to_free.size(); ++i) {
+ num_functional_writes += m_buffers_to_free[i]->functionalWrite(pkt);
+ }
+ return num_functional_writes;
+}
Switch *
SwitchParams::create()
diff --git a/src/mem/ruby/network/simple/Switch.hh b/src/mem/ruby/network/simple/Switch.hh
index 9946e5cc1..05e90f278 100644
--- a/src/mem/ruby/network/simple/Switch.hh
+++ b/src/mem/ruby/network/simple/Switch.hh
@@ -74,6 +74,9 @@ class Switch : public BasicRouter
void print(std::ostream& out) const;
void init_net_ptr(SimpleNetwork* net_ptr) { m_network_ptr = net_ptr; }
+ bool functionalRead(Packet *);
+ uint32_t functionalWrite(Packet *);
+
private:
// Private copy constructor and assignment operator
Switch(const Switch& obj);