network: basic link bw for garnet and simple networks

This patch ensures that both Garnet and the simple networks use the bw value
specified in the topology.  To do so, the patch generalizes the specification
of bw for basic links.  This value is then translated to the specific value
used by the simple and Garnet networks.  Since Garent does not support
non-uniformed link bandwidth, the patch also adds a check to ensure all bws are
equal.

--HG--
rename : src/mem/ruby/network/BasicLink.cc => src/mem/ruby/network/simple/SimpleLink.cc
rename : src/mem/ruby/network/BasicLink.hh => src/mem/ruby/network/simple/SimpleLink.hh
rename : src/mem/ruby/network/BasicLink.py => src/mem/ruby/network/simple/SimpleLink.py

5 files changed, 205 insertions, 4 deletions

diff --git a/src/mem/ruby/network/simple/SConscript b/src/mem/ruby/network/simple/SConscript
index c0fb84770..6bd836784 100644
--- a/src/mem/ruby/network/simple/SConscript
+++ b/src/mem/ruby/network/simple/SConscript
@@ -33,9 +33,11 @@ Import('*')
 if not env['RUBY']:
     Return()
 
+SimObject('SimpleLink.py')
 SimObject('SimpleNetwork.py')
 
 Source('PerfectSwitch.cc')
+Source('SimpleLink.cc')
 Source('SimpleNetwork.cc')
 Source('Switch.cc')
 Source('Throttle.cc')
diff --git a/src/mem/ruby/network/simple/SimpleLink.cc b/src/mem/ruby/network/simple/SimpleLink.cc
new file mode 100644
index 000000000..57ae6c79e
--- /dev/null
+++ b/src/mem/ruby/network/simple/SimpleLink.cc
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2011 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "mem/ruby/network/simple/SimpleLink.hh"
+
+SimpleExtLink::SimpleExtLink(const Params *p)
+    : BasicExtLink(p)
+{
+    // For the simple links, the bandwidth factor translates to the
+    // bandwidth multiplier.  The multipiler, in combination with the 
+    // endpoint bandwidth multiplier - message size multiplier ratio, 
+    // determines the link bandwidth in bytes 
+    m_bw_multiplier = p->bandwidth_factor;
+}
+
+void
+SimpleExtLink::print(std::ostream& out) const
+{
+    out << name();
+}
+
+SimpleExtLink *
+SimpleExtLinkParams::create()
+{
+    return new SimpleExtLink(this);
+}
+
+SimpleIntLink::SimpleIntLink(const Params *p)
+    : BasicIntLink(p)
+{
+    // For the simple links, the bandwidth factor translates to the
+    // bandwidth multiplier.  The multipiler, in combination with the 
+    // endpoint bandwidth multiplier - message size multiplier ratio, 
+    // determines the link bandwidth in bytes 
+    m_bw_multiplier = p->bandwidth_factor;
+}
+
+void
+SimpleIntLink::print(std::ostream& out) const
+{
+    out << name();
+}
+
+SimpleIntLink *
+SimpleIntLinkParams::create()
+{
+    return new SimpleIntLink(this);
+}
diff --git a/src/mem/ruby/network/simple/SimpleLink.hh b/src/mem/ruby/network/simple/SimpleLink.hh
new file mode 100644
index 000000000..ed98ec776
--- /dev/null
+++ b/src/mem/ruby/network/simple/SimpleLink.hh
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2011 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MEM_RUBY_NETWORK_SIMPLE_LINK_HH__
+#define __MEM_RUBY_NETWORK_SIMPLE_LINK_HH__
+
+#include <iostream>
+#include <string>
+#include <vector>
+
+#include "params/SimpleExtLink.hh"
+#include "params/SimpleIntLink.hh"
+#include "mem/ruby/network/BasicLink.hh"
+
+class SimpleExtLink : public BasicExtLink
+{
+  public:
+    typedef SimpleExtLinkParams Params;
+    SimpleExtLink(const Params *p);
+    const Params *params() const { return (const Params *)_params; }
+
+    friend class Topology;
+    void print(std::ostream& out) const;
+
+    int m_bw_multiplier;
+};
+
+inline std::ostream&
+operator<<(std::ostream& out, const SimpleExtLink& obj)
+{
+    obj.print(out);
+    out << std::flush;
+    return out;
+}
+
+class SimpleIntLink : public BasicIntLink
+{
+  public:
+    typedef SimpleIntLinkParams Params;
+    SimpleIntLink(const Params *p);
+    const Params *params() const { return (const Params *)_params; }
+
+    friend class Topology;
+    void print(std::ostream& out) const;
+
+    int m_bw_multiplier;
+};
+
+inline std::ostream&
+operator<<(std::ostream& out, const SimpleIntLink& obj)
+{
+    obj.print(out);
+    out << std::flush;
+    return out;
+}
+
+#endif // __MEM_RUBY_NETWORK_SIMPLE_LINK_HH__
diff --git a/src/mem/ruby/network/simple/SimpleLink.py b/src/mem/ruby/network/simple/SimpleLink.py
new file mode 100644
index 000000000..55b21562e
--- /dev/null
+++ b/src/mem/ruby/network/simple/SimpleLink.py
@@ -0,0 +1,39 @@
+# Copyright (c) 2011 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+#          Brad Beckmann
+
+from m5.params import *
+from m5.proxy import *
+from m5.SimObject import SimObject
+from BasicLink import BasicIntLink, BasicExtLink
+
+class SimpleExtLink(BasicExtLink):
+    type = 'SimpleExtLink'
+
+class SimpleIntLink(BasicIntLink):
+    type = 'SimpleIntLink'
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc b/src/mem/ruby/network/simple/SimpleNetwork.cc
index 15107b17f..8829b2eb5 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc
@@ -36,6 +36,7 @@
 #include "mem/ruby/buffers/MessageBuffer.hh"
 #include "mem/ruby/common/NetDest.hh"
 #include "mem/ruby/network/BasicLink.hh"
+#include "mem/ruby/network/simple/SimpleLink.hh"
 #include "mem/ruby/network/simple/SimpleNetwork.hh"
 #include "mem/ruby/network/simple/Switch.hh"
 #include "mem/ruby/network/simple/Throttle.hh"
@@ -148,10 +149,12 @@ SimpleNetwork::makeOutLink(SwitchID src, NodeID dest, BasicLink* link,
         return;
     }
 
+    SimpleExtLink *simple_link = safe_cast<SimpleExtLink*>(link);
+
     m_switch_ptr_vector[src]->addOutPort(m_fromNetQueues[dest],
                                          routing_table_entry,
-                                         link->m_latency,
-                                         link->m_bw_multiplier);
+                                         simple_link->m_latency,
+                                         simple_link->m_bw_multiplier);
 
     m_endpoint_switches[dest] = m_switch_ptr_vector[src];
 }
@@ -198,10 +201,12 @@ SimpleNetwork::makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link,
         m_buffers_to_free.push_back(buffer_ptr);
     }
     // Connect it to the two switches
+    SimpleIntLink *simple_link = safe_cast<SimpleIntLink*>(link);
+
     m_switch_ptr_vector[dest]->addInPort(queues);
     m_switch_ptr_vector[src]->addOutPort(queues, routing_table_entry,
-                                         link->m_latency, 
-                                         link->m_bw_multiplier);
+                                         simple_link->m_latency, 
+                                         simple_link->m_bw_multiplier);
 }
 
 void