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authorNilay Vaish <nilay@cs.wisc.edu>2015-09-16 11:59:56 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-09-16 11:59:56 -0500
commitcd9e4458139658c4ce8f038e3a44bdecd17fa75d (patch)
treec7403c142a9bf36869f75016c683b9c7ef731399 /src/mem/ruby/network/simple
parent78a1245b4115373856514eacf2264141e6cd4aca (diff)
downloadgem5-cd9e4458139658c4ce8f038e3a44bdecd17fa75d.tar.xz
ruby: message buffer, timer table: significant changes
This patch changes MessageBuffer and TimerTable, two structures used for buffering messages by components in ruby. These structures would no longer maintain pointers to clock objects. Functions in these structures have been changed to take as input current time in Tick. Similarly, these structures will not operate on Cycle valued latencies for different operations. The corresponding functions would need to be provided with these latencies by components invoking the relevant functions. These latencies should also be in Ticks. I felt the need for these changes while trying to speed up ruby. The ultimate aim is to eliminate Consumer class and replace it with an EventManager object in the MessageBuffer and TimerTable classes. This object would be used for scheduling events. The event itself would contain information on the object and function to be invoked. In hindsight, it seems I should have done this while I was moving away from use of a single global clock in the memory system. That change led to introduction of clock objects that replaced the global clock object. It never crossed my mind that having clock object pointers is not a good design. And now I really don't like the fact that we have separate consumer, receiver and sender pointers in message buffers.
Diffstat (limited to 'src/mem/ruby/network/simple')
-rw-r--r--src/mem/ruby/network/simple/PerfectSwitch.cc12
-rw-r--r--src/mem/ruby/network/simple/SimpleNetwork.py6
-rw-r--r--src/mem/ruby/network/simple/Switch.cc13
-rw-r--r--src/mem/ruby/network/simple/Throttle.cc20
4 files changed, 19 insertions, 32 deletions
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.cc b/src/mem/ruby/network/simple/PerfectSwitch.cc
index 697357ccb..301d453c5 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.cc
+++ b/src/mem/ruby/network/simple/PerfectSwitch.cc
@@ -144,8 +144,9 @@ PerfectSwitch::operateMessageBuffer(MessageBuffer *buffer, int incoming,
// temporary vectors to store the routing results
vector<LinkID> output_links;
vector<NetDest> output_link_destinations;
+ Tick current_time = m_switch->clockEdge();
- while (buffer->isReady()) {
+ while (buffer->isReady(current_time)) {
DPRINTF(RubyNetwork, "incoming: %d\n", incoming);
// Peek at message
@@ -176,7 +177,7 @@ PerfectSwitch::operateMessageBuffer(MessageBuffer *buffer, int incoming,
for (int out = 0; out < m_out.size(); out++) {
int out_queue_length = 0;
for (int v = 0; v < m_virtual_networks; v++) {
- out_queue_length += m_out[out][v]->getSize();
+ out_queue_length += m_out[out][v]->getSize(current_time);
}
int value =
(out_queue_length << 8) |
@@ -220,7 +221,7 @@ PerfectSwitch::operateMessageBuffer(MessageBuffer *buffer, int incoming,
for (int i = 0; i < output_links.size(); i++) {
int outgoing = output_links[i];
- if (!m_out[outgoing][vnet]->areNSlotsAvailable(1))
+ if (!m_out[outgoing][vnet]->areNSlotsAvailable(1, current_time))
enough = false;
DPRINTF(RubyNetwork, "Checking if node is blocked ..."
@@ -251,7 +252,7 @@ PerfectSwitch::operateMessageBuffer(MessageBuffer *buffer, int incoming,
}
// Dequeue msg
- buffer->dequeue();
+ buffer->dequeue(current_time);
m_pending_message_count[vnet]--;
// Enqueue it - for all outgoing queues
@@ -273,7 +274,8 @@ PerfectSwitch::operateMessageBuffer(MessageBuffer *buffer, int incoming,
"inport[%d][%d] to outport [%d][%d].\n",
incoming, vnet, outgoing, vnet);
- m_out[outgoing][vnet]->enqueue(msg_ptr);
+ m_out[outgoing][vnet]->enqueue(msg_ptr, current_time,
+ m_switch->cyclesToTicks(Cycles(1)));
}
}
}
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.py b/src/mem/ruby/network/simple/SimpleNetwork.py
index f4ec440a3..87de0fb46 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.py
+++ b/src/mem/ruby/network/simple/SimpleNetwork.py
@@ -41,9 +41,6 @@ class SimpleNetwork(RubyNetwork):
endpoint_bandwidth = Param.Int(1000, "bandwidth adjustment factor");
adaptive_routing = Param.Bool(False, "enable adaptive routing");
int_link_buffers = VectorParam.MessageBuffer("Buffers for int_links")
- # int_links do not recycle buffers, so this parameter is not used.
- # TODO: Move recycle_latency out of MessageBuffers and into controllers
- recycle_latency = Param.Cycles(0, "")
def setup_buffers(self):
# Note that all SimpleNetwork MessageBuffers are currently ordered
@@ -82,6 +79,3 @@ class Switch(BasicRouter):
virt_nets = Param.Int(Parent.number_of_virtual_networks,
"number of virtual networks")
port_buffers = VectorParam.MessageBuffer("Port buffers")
- # Ports do not recycle buffers, so this parameter is not used.
- # TODO: Move recycle_latency out of MessageBuffers and into controllers
- recycle_latency = Param.Cycles(0, "")
diff --git a/src/mem/ruby/network/simple/Switch.cc b/src/mem/ruby/network/simple/Switch.cc
index b9d0b8010..0951ef138 100644
--- a/src/mem/ruby/network/simple/Switch.cc
+++ b/src/mem/ruby/network/simple/Switch.cc
@@ -69,12 +69,6 @@ void
Switch::addInPort(const vector<MessageBuffer*>& in)
{
m_perfect_switch->addInPort(in);
-
- for (auto& it : in) {
- if (it != nullptr) {
- it->setReceiver(this);
- }
- }
}
void
@@ -95,17 +89,10 @@ Switch::addOutPort(const vector<MessageBuffer*>& out,
vector<MessageBuffer*> intermediateBuffers;
for (int i = 0; i < out.size(); ++i) {
- if (out[i] != nullptr) {
- out[i]->setSender(this);
- }
-
assert(m_num_connected_buffers < m_port_buffers.size());
MessageBuffer* buffer_ptr = m_port_buffers[m_num_connected_buffers];
m_num_connected_buffers++;
intermediateBuffers.push_back(buffer_ptr);
-
- buffer_ptr->setSender(this);
- buffer_ptr->setReceiver(this);
}
// Hook the queues to the PerfectSwitch
diff --git a/src/mem/ruby/network/simple/Throttle.cc b/src/mem/ruby/network/simple/Throttle.cc
index 01d1f6fbe..3863ab944 100644
--- a/src/mem/ruby/network/simple/Throttle.cc
+++ b/src/mem/ruby/network/simple/Throttle.cc
@@ -94,14 +94,16 @@ Throttle::operateVnet(int vnet, int &bw_remaining, bool &schedule_wakeup,
if (out == nullptr || in == nullptr) {
return;
}
- assert(m_units_remaining[vnet] >= 0);
- while (bw_remaining > 0 && (in->isReady() || m_units_remaining[vnet] > 0) &&
- out->areNSlotsAvailable(1)) {
+ assert(m_units_remaining[vnet] >= 0);
+ Tick current_time = m_switch->clockEdge();
+ while (bw_remaining > 0 && (in->isReady(current_time) ||
+ m_units_remaining[vnet] > 0) &&
+ out->areNSlotsAvailable(1, current_time)) {
// See if we are done transferring the previous message on
// this virtual network
- if (m_units_remaining[vnet] == 0 && in->isReady()) {
+ if (m_units_remaining[vnet] == 0 && in->isReady(current_time)) {
// Find the size of the message we are moving
MsgPtr msg_ptr = in->peekMsgPtr();
Message *net_msg_ptr = msg_ptr.get();
@@ -114,8 +116,9 @@ Throttle::operateVnet(int vnet, int &bw_remaining, bool &schedule_wakeup,
m_ruby_system->curCycle());
// Move the message
- in->dequeue();
- out->enqueue(msg_ptr, m_link_latency);
+ in->dequeue(current_time);
+ out->enqueue(msg_ptr, current_time,
+ m_switch->cyclesToTicks(m_link_latency));
// Count the message
m_msg_counts[net_msg_ptr->getMessageSize()][vnet]++;
@@ -128,8 +131,9 @@ Throttle::operateVnet(int vnet, int &bw_remaining, bool &schedule_wakeup,
bw_remaining = max(0, -diff);
}
- if (bw_remaining > 0 && (in->isReady() || m_units_remaining[vnet] > 0) &&
- !out->areNSlotsAvailable(1)) {
+ if (bw_remaining > 0 && (in->isReady(current_time) ||
+ m_units_remaining[vnet] > 0) &&
+ !out->areNSlotsAvailable(1, current_time)) {
DPRINTF(RubyNetwork, "vnet: %d", vnet);
// schedule me to wakeup again because I'm waiting for my