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author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-02-01 14:27:16 -0800 |
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committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-02-01 14:27:16 -0800 |
commit | 1d4c3ecdc347f42882a3d2f3c87dcd7725fda2e5 (patch) | |
tree | 46908d3b58a389a8ec6a60e4cb3866b0d1e9d8e8 /src/mem/ruby/network | |
parent | db2ecbb6b6eb8d5126c5f13b8a3af5d792487279 (diff) | |
download | gem5-1d4c3ecdc347f42882a3d2f3c87dcd7725fda2e5.tar.xz |
ruby: Added FS support to the simple mesh topology
Added full-system support to the simple mesh toplogy by allowing dma contrllers
to be attached to router zero in the network.
Diffstat (limited to 'src/mem/ruby/network')
-rw-r--r-- | src/mem/ruby/network/Network.py | 23 |
1 files changed, 21 insertions, 2 deletions
diff --git a/src/mem/ruby/network/Network.py b/src/mem/ruby/network/Network.py index 01ebfff70..619196591 100644 --- a/src/mem/ruby/network/Network.py +++ b/src/mem/ruby/network/Network.py @@ -70,21 +70,40 @@ def makeMesh(nodes, num_routers, num_rows): # Also, obviously the number or rows must be <= the number of routers # cntrls_per_router, remainder = divmod(len(nodes), num_routers) - assert(remainder == 0) assert(num_rows <= num_routers) num_columns = int(num_routers / num_rows) assert(num_columns * num_rows == num_routers) # + # Add all but the remainder nodes to the list of nodes to be uniformly + # distributed across the network. + # + network_nodes = [] + remainder_nodes = [] + for node_index in xrange(len(nodes)): + if node_index < (len(nodes) - remainder): + network_nodes.append(nodes[node_index]) + else: + remainder_nodes.append(nodes[node_index]) + + # # Connect each node to the appropriate router # ext_links = [] - for (i, n) in enumerate(nodes): + for (i, n) in enumerate(network_nodes): cntrl_level, router_id = divmod(i, num_routers) assert(cntrl_level < cntrls_per_router) ext_links.append(ExtLink(ext_node=n, int_node=router_id)) # + # Connect the remainding nodes to router 0. These should only be DMA nodes. + # + for (i, node) in enumerate(remainder_nodes): + assert(node.type == 'DMA_Controller') + assert(i < remainder) + ext_links.append(ExtLink(ext_node=node, int_node=0)) + + # # Create the mesh links. First row (east-west) links then column # (north-south) links # |