network: basic link bw for garnet and simple networks

This patch ensures that both Garnet and the simple networks use the bw value
specified in the topology.  To do so, the patch generalizes the specification
of bw for basic links.  This value is then translated to the specific value
used by the simple and Garnet networks.  Since Garent does not support
non-uniformed link bandwidth, the patch also adds a check to ensure all bws are
equal.

--HG--
rename : src/mem/ruby/network/BasicLink.cc => src/mem/ruby/network/simple/SimpleLink.cc
rename : src/mem/ruby/network/BasicLink.hh => src/mem/ruby/network/simple/SimpleLink.hh
rename : src/mem/ruby/network/BasicLink.py => src/mem/ruby/network/simple/SimpleLink.py

17 files changed, 247 insertions, 19 deletions

diff --git a/src/mem/ruby/network/BasicLink.cc b/src/mem/ruby/network/BasicLink.cc
index 907a04f39..292e74e96 100644
--- a/src/mem/ruby/network/BasicLink.cc
+++ b/src/mem/ruby/network/BasicLink.cc
@@ -32,7 +32,7 @@ BasicLink::BasicLink(const Params *p)
     : SimObject(p)
 {
     m_latency = p->latency;
-    m_bw_multiplier = p->bw_multiplier;
+    m_bandwidth_factor = p->bandwidth_factor;
     m_weight = p->weight;
 }
 
diff --git a/src/mem/ruby/network/BasicLink.hh b/src/mem/ruby/network/BasicLink.hh
index c7359807f..11832f9c3 100644
--- a/src/mem/ruby/network/BasicLink.hh
+++ b/src/mem/ruby/network/BasicLink.hh
@@ -53,7 +53,7 @@ class BasicLink : public SimObject
     void print(std::ostream& out) const;
 
     int m_latency;
-    int m_bw_multiplier;
+    int m_bandwidth_factor;
     int m_weight;
 };
 
diff --git a/src/mem/ruby/network/BasicLink.py b/src/mem/ruby/network/BasicLink.py
index 53df4d57e..fb73f9ac7 100644
--- a/src/mem/ruby/network/BasicLink.py
+++ b/src/mem/ruby/network/BasicLink.py
@@ -34,17 +34,21 @@ class BasicLink(SimObject):
     type = 'BasicLink'
     link_id = Param.Int("ID in relation to other links")
     latency = Param.Int(1, "latency")
-    bw_multiplier = Param.Int("simple network bw constant, usually in bytes")
+    # The following banwidth factor does not translate to the same value for
+    # both the simple and Garnet models.  For the most part, the bandwidth
+    # factor is the width of the link in bytes, expect for certain situations
+    # with regard to the simple network.
+    bandwidth_factor = Param.Int("generic bandwidth factor, usually in bytes")
     weight = Param.Int(1, "used to restrict routing in shortest path analysis")
 
 class BasicExtLink(BasicLink):
     type = 'BasicExtLink'
     ext_node = Param.RubyController("External node")
     int_node = Param.BasicRouter("ID of internal node")
-    bw_multiplier = 64
+    bandwidth_factor = 64
 
 class BasicIntLink(BasicLink):
     type = 'BasicIntLink'
     node_a = Param.BasicRouter("Router on one end")
     node_b = Param.BasicRouter("Router on other end")
-    bw_multiplier = 16
+    bandwidth_factor = 16
diff --git a/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc b/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
index 19b4c3d04..6c5e57103 100644
--- a/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
+++ b/src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
@@ -28,16 +28,37 @@
  * Authors: Niket Agarwal
  */
 
+#include "mem/ruby/network/BasicLink.hh"
+#include "mem/ruby/network/Topology.hh"
 #include "mem/ruby/network/garnet/BaseGarnetNetwork.hh"
 
 BaseGarnetNetwork::BaseGarnetNetwork(const Params *p)
     : Network(p)
 {
-    m_flit_size = p->flit_size;
+    m_ni_flit_size = p->ni_flit_size;
     m_number_of_pipe_stages = p->number_of_pipe_stages;
     m_vcs_per_class = p->vcs_per_class;
     m_buffers_per_data_vc = p->buffers_per_data_vc;
     m_buffers_per_ctrl_vc = p->buffers_per_ctrl_vc;
+
+    // Currently Garnet only supports uniform bandwidth for all
+    // links and network interfaces.
+    for (std::vector<BasicExtLink*>::const_iterator i = 
+             m_topology_ptr->params()->ext_links.begin();
+         i != m_topology_ptr->params()->ext_links.end(); ++i) {
+        BasicExtLink* ext_link = (*i);
+        if (ext_link->params()->bandwidth_factor != m_ni_flit_size) {
+            fatal("Garnet only supports uniform bw across all links and NIs\n");
+        }
+    }
+    for (std::vector<BasicIntLink*>::const_iterator i = 
+             m_topology_ptr->params()->int_links.begin();
+         i != m_topology_ptr->params()->int_links.end(); ++i) {
+        BasicIntLink* int_link = (*i);
+        if (int_link->params()->bandwidth_factor != m_ni_flit_size) {
+            fatal("Garnet only supports uniform bw across all links and NIs\n");
+        }
+    }
 }
 
 void
diff --git a/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh b/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh
index 81b77ceea..4ff04b683 100644
--- a/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh
+++ b/src/mem/ruby/network/garnet/BaseGarnetNetwork.hh
@@ -48,14 +48,14 @@ class BaseGarnetNetwork : public Network
     BaseGarnetNetwork(const Params *p);
 
     void init();
-    int getFlitSize() {return m_flit_size; }
+    int getNiFlitSize() {return m_ni_flit_size; }
     int getNumPipeStages() {return m_number_of_pipe_stages; }
     int getVCsPerClass() {return m_vcs_per_class; }
     int getBuffersPerDataVC() {return m_buffers_per_data_vc; }
     int getBuffersPerCtrlVC() {return m_buffers_per_ctrl_vc; }
 
   protected:
-    int m_flit_size;
+    int m_ni_flit_size;
     int m_number_of_pipe_stages;
     int m_vcs_per_class;
     int m_buffers_per_data_vc;
diff --git a/src/mem/ruby/network/garnet/BaseGarnetNetwork.py b/src/mem/ruby/network/garnet/BaseGarnetNetwork.py
index 3594e93b6..d2366ed1a 100644
--- a/src/mem/ruby/network/garnet/BaseGarnetNetwork.py
+++ b/src/mem/ruby/network/garnet/BaseGarnetNetwork.py
@@ -34,7 +34,7 @@ from Network import RubyNetwork
 class BaseGarnetNetwork(RubyNetwork):
     type = 'BaseGarnetNetwork'
     abstract = True
-    flit_size = Param.Int(16, "flit size in bytes")
+    ni_flit_size = Param.Int(16, "network interface flit size in bytes")
     number_of_pipe_stages = Param.Int(4, "router pipeline stages");
     vcs_per_class = Param.Int(4, "virtual channels per message class");
     buffers_per_data_vc = Param.Int(4, "buffers per data virtual channel");
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
index 941746cbc..363ff2e44 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
@@ -41,7 +41,8 @@ class NetworkLink_d(SimObject):
                               "virtual channels per message class")
     virt_nets = Param.Int(Parent.number_of_virtual_networks,
                           "number of virtual networks")
-    channel_width = Param.Int(Parent.flit_size, "channel width == flit size")
+    channel_width = Param.Int(Parent.bandwidth_factor,
+                              "channel width == bw factor")
 
 class CreditLink_d(NetworkLink_d):
     type = 'CreditLink_d'
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py
index 92e49b328..1a216abb9 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py
@@ -39,6 +39,6 @@ class GarnetRouter_d(BasicRouter):
                               "virtual channels per message class")
     virt_nets = Param.Int(Parent.number_of_virtual_networks,
                           "number of virtual networks")
-    flit_width = Param.Int(Parent.flit_size, "flit width == flit size")
+    flit_width = Param.Int(Parent.ni_flit_size, "flit width == flit size")
 
 
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
index 71fefa264..0dd51019c 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
@@ -129,7 +129,7 @@ NetworkInterface_d::flitisizeMessage(MsgPtr msg_ptr, int vnet)
     // Number of flits is dependent on the link bandwidth available.
     // This is expressed in terms of bytes/cycle or the flit size
     int num_flits = (int) ceil((double) m_net_ptr->MessageSizeType_to_int(
-        net_msg_ptr->getMessageSize())/m_net_ptr->getFlitSize() );
+        net_msg_ptr->getMessageSize())/m_net_ptr->getNiFlitSize());
 
     // loop to convert all multicast messages into unicast messages
     for (int ctr = 0; ctr < dest_nodes.size(); ctr++) {
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
index 45c56fa9e..4077f30e6 100644
--- a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
@@ -41,7 +41,8 @@ class NetworkLink(SimObject):
                               "virtual channels per message class")
     virt_nets = Param.Int(Parent.number_of_virtual_networks,
                           "number of virtual networks")
-    channel_width = Param.Int(Parent.flit_size, "channel width == flit size")
+    channel_width = Param.Int(Parent.bandwidth_factor,
+                              "channel width == bw factor")
 
 # Interior fixed pipeline links between routers
 class GarnetIntLink(BasicIntLink):
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
index c35b7db38..1aabd375f 100644
--- a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
@@ -39,6 +39,6 @@ class GarnetRouter(BasicRouter):
                               "virtual channels per message class")
     virt_nets = Param.Int(Parent.number_of_virtual_networks,
                           "number of virtual networks")
-    flit_width = Param.Int(Parent.flit_size, "flit width == flit size")
+    flit_width = Param.Int(Parent.ni_flit_size, "flit width == flit size")
 
 
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
index de51a7284..df9f91c2d 100644
--- a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
@@ -127,7 +127,7 @@ NetworkInterface::flitisizeMessage(MsgPtr msg_ptr, int vnet)
     // This is expressed in terms of bytes/cycle or the flit size
 
     int num_flits = (int) ceil((double) m_net_ptr->MessageSizeType_to_int(
-                net_msg_ptr->getMessageSize())/m_net_ptr->getFlitSize() );
+                net_msg_ptr->getMessageSize())/m_net_ptr->getNiFlitSize());
 
     // loop to convert all multicast messages into unicast messages
     for (int ctr = 0; ctr < dest_nodes.size(); ctr++) {
diff --git a/src/mem/ruby/network/simple/SConscript b/src/mem/ruby/network/simple/SConscript
index c0fb84770..6bd836784 100644
--- a/src/mem/ruby/network/simple/SConscript
+++ b/src/mem/ruby/network/simple/SConscript
@@ -33,9 +33,11 @@ Import('*')
 if not env['RUBY']:
     Return()
 
+SimObject('SimpleLink.py')
 SimObject('SimpleNetwork.py')
 
 Source('PerfectSwitch.cc')
+Source('SimpleLink.cc')
 Source('SimpleNetwork.cc')
 Source('Switch.cc')
 Source('Throttle.cc')
diff --git a/src/mem/ruby/network/simple/SimpleLink.cc b/src/mem/ruby/network/simple/SimpleLink.cc
new file mode 100644
index 000000000..57ae6c79e
--- /dev/null
+++ b/src/mem/ruby/network/simple/SimpleLink.cc
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2011 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "mem/ruby/network/simple/SimpleLink.hh"
+
+SimpleExtLink::SimpleExtLink(const Params *p)
+    : BasicExtLink(p)
+{
+    // For the simple links, the bandwidth factor translates to the
+    // bandwidth multiplier.  The multipiler, in combination with the 
+    // endpoint bandwidth multiplier - message size multiplier ratio, 
+    // determines the link bandwidth in bytes 
+    m_bw_multiplier = p->bandwidth_factor;
+}
+
+void
+SimpleExtLink::print(std::ostream& out) const
+{
+    out << name();
+}
+
+SimpleExtLink *
+SimpleExtLinkParams::create()
+{
+    return new SimpleExtLink(this);
+}
+
+SimpleIntLink::SimpleIntLink(const Params *p)
+    : BasicIntLink(p)
+{
+    // For the simple links, the bandwidth factor translates to the
+    // bandwidth multiplier.  The multipiler, in combination with the 
+    // endpoint bandwidth multiplier - message size multiplier ratio, 
+    // determines the link bandwidth in bytes 
+    m_bw_multiplier = p->bandwidth_factor;
+}
+
+void
+SimpleIntLink::print(std::ostream& out) const
+{
+    out << name();
+}
+
+SimpleIntLink *
+SimpleIntLinkParams::create()
+{
+    return new SimpleIntLink(this);
+}
diff --git a/src/mem/ruby/network/simple/SimpleLink.hh b/src/mem/ruby/network/simple/SimpleLink.hh
new file mode 100644
index 000000000..ed98ec776
--- /dev/null
+++ b/src/mem/ruby/network/simple/SimpleLink.hh
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2011 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MEM_RUBY_NETWORK_SIMPLE_LINK_HH__
+#define __MEM_RUBY_NETWORK_SIMPLE_LINK_HH__
+
+#include <iostream>
+#include <string>
+#include <vector>
+
+#include "params/SimpleExtLink.hh"
+#include "params/SimpleIntLink.hh"
+#include "mem/ruby/network/BasicLink.hh"
+
+class SimpleExtLink : public BasicExtLink
+{
+  public:
+    typedef SimpleExtLinkParams Params;
+    SimpleExtLink(const Params *p);
+    const Params *params() const { return (const Params *)_params; }
+
+    friend class Topology;
+    void print(std::ostream& out) const;
+
+    int m_bw_multiplier;
+};
+
+inline std::ostream&
+operator<<(std::ostream& out, const SimpleExtLink& obj)
+{
+    obj.print(out);
+    out << std::flush;
+    return out;
+}
+
+class SimpleIntLink : public BasicIntLink
+{
+  public:
+    typedef SimpleIntLinkParams Params;
+    SimpleIntLink(const Params *p);
+    const Params *params() const { return (const Params *)_params; }
+
+    friend class Topology;
+    void print(std::ostream& out) const;
+
+    int m_bw_multiplier;
+};
+
+inline std::ostream&
+operator<<(std::ostream& out, const SimpleIntLink& obj)
+{
+    obj.print(out);
+    out << std::flush;
+    return out;
+}
+
+#endif // __MEM_RUBY_NETWORK_SIMPLE_LINK_HH__
diff --git a/src/mem/ruby/network/simple/SimpleLink.py b/src/mem/ruby/network/simple/SimpleLink.py
new file mode 100644
index 000000000..55b21562e
--- /dev/null
+++ b/src/mem/ruby/network/simple/SimpleLink.py
@@ -0,0 +1,39 @@
+# Copyright (c) 2011 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+#          Brad Beckmann
+
+from m5.params import *
+from m5.proxy import *
+from m5.SimObject import SimObject
+from BasicLink import BasicIntLink, BasicExtLink
+
+class SimpleExtLink(BasicExtLink):
+    type = 'SimpleExtLink'
+
+class SimpleIntLink(BasicIntLink):
+    type = 'SimpleIntLink'
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc b/src/mem/ruby/network/simple/SimpleNetwork.cc
index 15107b17f..8829b2eb5 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc
@@ -36,6 +36,7 @@
 #include "mem/ruby/buffers/MessageBuffer.hh"
 #include "mem/ruby/common/NetDest.hh"
 #include "mem/ruby/network/BasicLink.hh"
+#include "mem/ruby/network/simple/SimpleLink.hh"
 #include "mem/ruby/network/simple/SimpleNetwork.hh"
 #include "mem/ruby/network/simple/Switch.hh"
 #include "mem/ruby/network/simple/Throttle.hh"
@@ -148,10 +149,12 @@ SimpleNetwork::makeOutLink(SwitchID src, NodeID dest, BasicLink* link,
         return;
     }
 
+    SimpleExtLink *simple_link = safe_cast<SimpleExtLink*>(link);
+
     m_switch_ptr_vector[src]->addOutPort(m_fromNetQueues[dest],
                                          routing_table_entry,
-                                         link->m_latency,
-                                         link->m_bw_multiplier);
+                                         simple_link->m_latency,
+                                         simple_link->m_bw_multiplier);
 
     m_endpoint_switches[dest] = m_switch_ptr_vector[src];
 }
@@ -198,10 +201,12 @@ SimpleNetwork::makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link,
         m_buffers_to_free.push_back(buffer_ptr);
     }
     // Connect it to the two switches
+    SimpleIntLink *simple_link = safe_cast<SimpleIntLink*>(link);
+
     m_switch_ptr_vector[dest]->addInPort(queues);
     m_switch_ptr_vector[src]->addOutPort(queues, routing_table_entry,
-                                         link->m_latency, 
-                                         link->m_bw_multiplier);
+                                         simple_link->m_latency, 
+                                         simple_link->m_bw_multiplier);
 }
 
 void