diff options
author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-08-20 11:46:12 -0700 |
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committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-08-20 11:46:12 -0700 |
commit | 4b4e7259218cf244a61e71a4d42ff63d2a2b98bd (patch) | |
tree | eea64ee4c648a7f7747861ebdc4a336d6fe35c54 /src/mem/ruby/profiler/Profiler.cc | |
parent | 9fb4381ddcc2663f77542855cbc026ba8cfb17a6 (diff) | |
download | gem5-4b4e7259218cf244a61e71a4d42ff63d2a2b98bd.tar.xz |
ruby: Reincarnated the responding machine profiling
This patch adds back to ruby the capability to understand the response time
for messages that hit in different levels of the cache heirarchy.
Specifically add support for the MI_example, MOESI_hammer, and MOESI_CMP_token
protocols.
Diffstat (limited to 'src/mem/ruby/profiler/Profiler.cc')
-rw-r--r-- | src/mem/ruby/profiler/Profiler.cc | 22 |
1 files changed, 13 insertions, 9 deletions
diff --git a/src/mem/ruby/profiler/Profiler.cc b/src/mem/ruby/profiler/Profiler.cc index 2b844ef9d..753fdd230 100644 --- a/src/mem/ruby/profiler/Profiler.cc +++ b/src/mem/ruby/profiler/Profiler.cc @@ -574,23 +574,27 @@ Profiler::bankBusy() // non-zero cycle demand request void -Profiler::missLatency(Time t, RubyRequestType type) +Profiler::missLatency(Time cycles, + RubyRequestType type, + const GenericMachineType respondingMach) { - m_allMissLatencyHistogram.add(t); - m_missLatencyHistograms[type].add(t); + m_allMissLatencyHistogram.add(cycles); + m_missLatencyHistograms[type].add(cycles); + m_machLatencyHistograms[respondingMach].add(cycles); } // non-zero cycle prefetch request void -Profiler::swPrefetchLatency(Time t, CacheRequestType type, - GenericMachineType respondingMach) +Profiler::swPrefetchLatency(Time cycles, + CacheRequestType type, + const GenericMachineType respondingMach) { - m_allSWPrefetchLatencyHistogram.add(t); - m_SWPrefetchLatencyHistograms[type].add(t); - m_SWPrefetchMachLatencyHistograms[respondingMach].add(t); + m_allSWPrefetchLatencyHistogram.add(cycles); + m_SWPrefetchLatencyHistograms[type].add(cycles); + m_SWPrefetchMachLatencyHistograms[respondingMach].add(cycles); if (respondingMach == GenericMachineType_Directory || respondingMach == GenericMachineType_NUM) { - m_SWPrefetchL2MissLatencyHistogram.add(t); + m_SWPrefetchL2MissLatencyHistogram.add(cycles); } } |