summaryrefslogtreecommitdiff
path: root/src/mem/ruby/profiler
diff options
context:
space:
mode:
authorBrad Beckmann <Brad.Beckmann@amd.com>2010-08-20 11:46:12 -0700
committerBrad Beckmann <Brad.Beckmann@amd.com>2010-08-20 11:46:12 -0700
commit4b4e7259218cf244a61e71a4d42ff63d2a2b98bd (patch)
treeeea64ee4c648a7f7747861ebdc4a336d6fe35c54 /src/mem/ruby/profiler
parent9fb4381ddcc2663f77542855cbc026ba8cfb17a6 (diff)
downloadgem5-4b4e7259218cf244a61e71a4d42ff63d2a2b98bd.tar.xz
ruby: Reincarnated the responding machine profiling
This patch adds back to ruby the capability to understand the response time for messages that hit in different levels of the cache heirarchy. Specifically add support for the MI_example, MOESI_hammer, and MOESI_CMP_token protocols.
Diffstat (limited to 'src/mem/ruby/profiler')
-rw-r--r--src/mem/ruby/profiler/Profiler.cc22
-rw-r--r--src/mem/ruby/profiler/Profiler.hh12
2 files changed, 22 insertions, 12 deletions
diff --git a/src/mem/ruby/profiler/Profiler.cc b/src/mem/ruby/profiler/Profiler.cc
index 2b844ef9d..753fdd230 100644
--- a/src/mem/ruby/profiler/Profiler.cc
+++ b/src/mem/ruby/profiler/Profiler.cc
@@ -574,23 +574,27 @@ Profiler::bankBusy()
// non-zero cycle demand request
void
-Profiler::missLatency(Time t, RubyRequestType type)
+Profiler::missLatency(Time cycles,
+ RubyRequestType type,
+ const GenericMachineType respondingMach)
{
- m_allMissLatencyHistogram.add(t);
- m_missLatencyHistograms[type].add(t);
+ m_allMissLatencyHistogram.add(cycles);
+ m_missLatencyHistograms[type].add(cycles);
+ m_machLatencyHistograms[respondingMach].add(cycles);
}
// non-zero cycle prefetch request
void
-Profiler::swPrefetchLatency(Time t, CacheRequestType type,
- GenericMachineType respondingMach)
+Profiler::swPrefetchLatency(Time cycles,
+ CacheRequestType type,
+ const GenericMachineType respondingMach)
{
- m_allSWPrefetchLatencyHistogram.add(t);
- m_SWPrefetchLatencyHistograms[type].add(t);
- m_SWPrefetchMachLatencyHistograms[respondingMach].add(t);
+ m_allSWPrefetchLatencyHistogram.add(cycles);
+ m_SWPrefetchLatencyHistograms[type].add(cycles);
+ m_SWPrefetchMachLatencyHistograms[respondingMach].add(cycles);
if (respondingMach == GenericMachineType_Directory ||
respondingMach == GenericMachineType_NUM) {
- m_SWPrefetchL2MissLatencyHistogram.add(t);
+ m_SWPrefetchL2MissLatencyHistogram.add(cycles);
}
}
diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh
index 20491cab7..de9834f05 100644
--- a/src/mem/ruby/profiler/Profiler.hh
+++ b/src/mem/ruby/profiler/Profiler.hh
@@ -133,9 +133,15 @@ class Profiler : public SimObject, public Consumer
void controllerBusy(MachineID machID);
void bankBusy();
- void missLatency(Time t, RubyRequestType type);
- void swPrefetchLatency(Time t, CacheRequestType type,
- GenericMachineType respondingMach);
+
+ void missLatency(Time t,
+ RubyRequestType type,
+ const GenericMachineType respondingMach);
+
+ void swPrefetchLatency(Time t,
+ CacheRequestType type,
+ const GenericMachineType respondingMach);
+
void sequencerRequests(int num) { m_sequencer_requests.add(num); }
void profileTransition(const std::string& component, NodeID version,