Ruby: Convert CacheRequestType to RubyRequestType

This patch converts CacheRequestType to RubyRequestType so that both the
protocol dependent and independent code makes use of the same request type.

8 files changed, 24 insertions, 24 deletions

diff --git a/src/mem/ruby/profiler/AccessTraceForAddress.cc b/src/mem/ruby/profiler/AccessTraceForAddress.cc
index 9cbf71163..a61c7329f 100644
--- a/src/mem/ruby/profiler/AccessTraceForAddress.cc
+++ b/src/mem/ruby/profiler/AccessTraceForAddress.cc
@@ -58,17 +58,17 @@ AccessTraceForAddress::print(std::ostream& out) const
 }
 
 void
-AccessTraceForAddress::update(CacheRequestType type,
+AccessTraceForAddress::update(RubyRequestType type,
                               RubyAccessMode access_mode, NodeID cpu,
                               bool sharing_miss)
 {
     m_touched_by.add(cpu);
     m_total++;
-    if(type == CacheRequestType_ATOMIC) {
+    if(type == RubyRequestType_ATOMIC) {
         m_atomics++;
-    } else if(type == CacheRequestType_LD){
+    } else if(type == RubyRequestType_LD){
         m_loads++;
-    } else if (type == CacheRequestType_ST){
+    } else if (type == RubyRequestType_ST){
         m_stores++;
     } else {
         //  ERROR_MSG("Trying to add invalid access to trace");
diff --git a/src/mem/ruby/profiler/AccessTraceForAddress.hh b/src/mem/ruby/profiler/AccessTraceForAddress.hh
index 9b6db2376..228ebcade 100644
--- a/src/mem/ruby/profiler/AccessTraceForAddress.hh
+++ b/src/mem/ruby/profiler/AccessTraceForAddress.hh
@@ -32,7 +32,7 @@
 #include <iostream>
 
 #include "mem/protocol/RubyAccessMode.hh"
-#include "mem/protocol/CacheRequestType.hh"
+#include "mem/protocol/RubyRequestType.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Global.hh"
 #include "mem/ruby/common/Set.hh"
@@ -50,7 +50,7 @@ class AccessTraceForAddress
     ~AccessTraceForAddress();
 
     void setAddress(const Address& addr) { m_addr = addr; }
-    void update(CacheRequestType type, RubyAccessMode access_mode, NodeID cpu,
+    void update(RubyRequestType type, RubyAccessMode access_mode, NodeID cpu,
                 bool sharing_miss);
     int getTotal() const;
     int getSharing() const { return m_sharing; }
diff --git a/src/mem/ruby/profiler/AddressProfiler.cc b/src/mem/ruby/profiler/AddressProfiler.cc
index 6ec0e20ba..722845c45 100644
--- a/src/mem/ruby/profiler/AddressProfiler.cc
+++ b/src/mem/ruby/profiler/AddressProfiler.cc
@@ -257,7 +257,7 @@ AddressProfiler::profileGetX(const Address& datablock, const Address& PC,
     m_getx_sharing_histogram.add(num_indirections);
     bool indirection_miss = (num_indirections > 0);
 
-    addTraceSample(datablock, PC, CacheRequestType_ST, RubyAccessMode(0),
+    addTraceSample(datablock, PC, RubyRequestType_ST, RubyAccessMode(0),
                    requestor, indirection_miss);
 }
 
@@ -274,13 +274,13 @@ AddressProfiler::profileGetS(const Address& datablock, const Address& PC,
     m_gets_sharing_histogram.add(num_indirections);
     bool indirection_miss = (num_indirections > 0);
 
-    addTraceSample(datablock, PC, CacheRequestType_LD, RubyAccessMode(0),
+    addTraceSample(datablock, PC, RubyRequestType_LD, RubyAccessMode(0),
                    requestor, indirection_miss);
 }
 
 void
 AddressProfiler::addTraceSample(Address data_addr, Address pc_addr,
-                                CacheRequestType type,
+                                RubyRequestType type,
                                 RubyAccessMode access_mode, NodeID id,
                                 bool sharing_miss)
 {
diff --git a/src/mem/ruby/profiler/AddressProfiler.hh b/src/mem/ruby/profiler/AddressProfiler.hh
index fe822c116..471feaaa5 100644
--- a/src/mem/ruby/profiler/AddressProfiler.hh
+++ b/src/mem/ruby/profiler/AddressProfiler.hh
@@ -55,7 +55,7 @@ class AddressProfiler
     void clearStats();
 
     void addTraceSample(Address data_addr, Address pc_addr,
-                        CacheRequestType type, RubyAccessMode access_mode,
+                        RubyRequestType type, RubyAccessMode access_mode,
                         NodeID id, bool sharing_miss);
     void profileRetry(const Address& data_addr, AccessType type, int count);
     void profileGetX(const Address& datablock, const Address& PC,
diff --git a/src/mem/ruby/profiler/CacheProfiler.cc b/src/mem/ruby/profiler/CacheProfiler.cc
index fcad227fb..fdb4581bb 100644
--- a/src/mem/ruby/profiler/CacheProfiler.cc
+++ b/src/mem/ruby/profiler/CacheProfiler.cc
@@ -33,7 +33,7 @@
 using namespace std;
 
 CacheProfiler::CacheProfiler(const string& description)
-    : m_cacheRequestType(int(CacheRequestType_NUM)), m_genericRequestType(int(GenericRequestType_NUM))
+    : m_cacheRequestType(int(RubyRequestType_NUM)), m_genericRequestType(int(GenericRequestType_NUM))
 {
     m_description = description;
 
@@ -59,7 +59,7 @@ CacheProfiler::printStats(ostream& out) const
 
     int requests = 0;
 
-    for (int i = 0; i < int(CacheRequestType_NUM); i++) {
+    for (int i = 0; i < int(RubyRequestType_NUM); i++) {
         requests += m_cacheRequestType[i];
     }
 
@@ -70,10 +70,10 @@ CacheProfiler::printStats(ostream& out) const
     assert(m_misses == requests);
 
     if (requests > 0) {
-        for (int i = 0; i < int(CacheRequestType_NUM); i++) {
+        for (int i = 0; i < int(RubyRequestType_NUM); i++) {
             if (m_cacheRequestType[i] > 0) {
                 out << description << "_request_type_"
-                    << CacheRequestType_to_string(CacheRequestType(i))
+                    << RubyRequestType_to_string(RubyRequestType(i))
                     << ":   "
                     << 100.0 * (double)m_cacheRequestType[i] /
                     (double)requests
@@ -111,7 +111,7 @@ CacheProfiler::printStats(ostream& out) const
 void
 CacheProfiler::clearStats()
 {
-    for (int i = 0; i < int(CacheRequestType_NUM); i++) {
+    for (int i = 0; i < int(RubyRequestType_NUM); i++) {
         m_cacheRequestType[i] = 0;
     }
     for (int i = 0; i < int(GenericRequestType_NUM); i++) {
@@ -128,7 +128,7 @@ CacheProfiler::clearStats()
 }
 
 void
-CacheProfiler::addCacheStatSample(CacheRequestType requestType,
+CacheProfiler::addCacheStatSample(RubyRequestType requestType,
                                   RubyAccessMode accessType,
                                   PrefetchBit pfBit)
 {
diff --git a/src/mem/ruby/profiler/CacheProfiler.hh b/src/mem/ruby/profiler/CacheProfiler.hh
index 9a8fdefb4..1ae6ba7a8 100644
--- a/src/mem/ruby/profiler/CacheProfiler.hh
+++ b/src/mem/ruby/profiler/CacheProfiler.hh
@@ -34,7 +34,7 @@
 #include <vector>
 
 #include "mem/protocol/RubyAccessMode.hh"
-#include "mem/protocol/CacheRequestType.hh"
+#include "mem/protocol/RubyRequestType.hh"
 #include "mem/protocol/GenericRequestType.hh"
 #include "mem/protocol/PrefetchBit.hh"
 #include "mem/ruby/common/Global.hh"
@@ -50,7 +50,7 @@ class CacheProfiler
     void printStats(std::ostream& out) const;
     void clearStats();
 
-    void addCacheStatSample(CacheRequestType requestType, 
+    void addCacheStatSample(RubyRequestType requestType,
                             RubyAccessMode type,
                             PrefetchBit pfBit);
 
diff --git a/src/mem/ruby/profiler/Profiler.cc b/src/mem/ruby/profiler/Profiler.cc
index 8596d04f1..8604d014f 100644
--- a/src/mem/ruby/profiler/Profiler.cc
+++ b/src/mem/ruby/profiler/Profiler.cc
@@ -320,7 +320,7 @@ Profiler::printStats(ostream& out, bool short_stats)
         out << "prefetch_latency: " << m_allSWPrefetchLatencyHistogram << endl;
         for (int i = 0; i < m_SWPrefetchLatencyHistograms.size(); i++) {
             if (m_SWPrefetchLatencyHistograms[i].size() > 0) {
-                out << "prefetch_latency_" << CacheRequestType(i) << ": "
+                out << "prefetch_latency_" << RubyRequestType(i) << ": "
                     << m_SWPrefetchLatencyHistograms[i] << endl;
             }
         }
@@ -500,7 +500,7 @@ Profiler::clearStats()
     m_dirFirstResponseToCompleteHistogram.clear(200);
     m_dirIncompleteTimes = 0;
 
-    m_SWPrefetchLatencyHistograms.resize(CacheRequestType_NUM);
+    m_SWPrefetchLatencyHistograms.resize(RubyRequestType_NUM);
     for (int i = 0; i < m_SWPrefetchLatencyHistograms.size(); i++) {
         m_SWPrefetchLatencyHistograms[i].clear(200);
     }
@@ -537,7 +537,7 @@ Profiler::clearStats()
 void
 Profiler::addAddressTraceSample(const CacheMsg& msg, NodeID id)
 {
-    if (msg.getType() != CacheRequestType_IFETCH) {
+    if (msg.getType() != RubyRequestType_IFETCH) {
         // Note: The following line should be commented out if you
         // want to use the special profiling that is part of the GS320
         // protocol
@@ -683,7 +683,7 @@ Profiler::missLatencyDir(Time issuedTime,
 // non-zero cycle prefetch request
 void
 Profiler::swPrefetchLatency(Time cycles, 
-                            CacheRequestType type,
+                            RubyRequestType type,
                             const GenericMachineType respondingMach)
 {
     m_allSWPrefetchLatencyHistogram.add(cycles);
diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh
index a3eb8cd71..8e3e7f547 100644
--- a/src/mem/ruby/profiler/Profiler.hh
+++ b/src/mem/ruby/profiler/Profiler.hh
@@ -53,7 +53,7 @@
 #include "base/hashmap.hh"
 #include "mem/protocol/RubyAccessMode.hh"
 #include "mem/protocol/AccessType.hh"
-#include "mem/protocol/CacheRequestType.hh"
+#include "mem/protocol/RubyRequestType.hh"
 #include "mem/protocol/GenericMachineType.hh"
 #include "mem/protocol/GenericRequestType.hh"
 #include "mem/protocol/PrefetchBit.hh"
@@ -150,7 +150,7 @@ class Profiler : public SimObject, public Consumer
                         Time completionTime);
     
     void swPrefetchLatency(Time t, 
-                           CacheRequestType type,
+                           RubyRequestType type,
                            const GenericMachineType respondingMach);
 
     void sequencerRequests(int num) { m_sequencer_requests.add(num); }