ruby: Fixed L2 cache miss profiling

Fixed L2 cache miss profiling for the MOESI_CMP_token protocol

2 files changed, 54 insertions, 17 deletions

diff --git a/src/mem/ruby/profiler/CacheProfiler.cc b/src/mem/ruby/profiler/CacheProfiler.cc
index 006617190..a969b9074 100644
--- a/src/mem/ruby/profiler/CacheProfiler.cc
+++ b/src/mem/ruby/profiler/CacheProfiler.cc
@@ -33,7 +33,7 @@
 using namespace std;
 
 CacheProfiler::CacheProfiler(const string& description)
-    : m_requestTypeVec(int(CacheRequestType_NUM))
+    : m_cacheRequestType(int(CacheRequestType_NUM)), m_genericRequestType(int(GenericRequestType_NUM))
 {
     m_description = description;
 
@@ -60,18 +60,33 @@ CacheProfiler::printStats(ostream& out) const
     int requests = 0;
 
     for (int i = 0; i < int(CacheRequestType_NUM); i++) {
-        requests += m_requestTypeVec[i];
+        requests += m_cacheRequestType[i];
+    }
+
+    for (int i = 0; i < int(GenericRequestType_NUM); i++) {
+        requests += m_genericRequestType[i];
     }
 
     assert(m_misses == requests);
 
     if (requests > 0) {
         for (int i = 0; i < int(CacheRequestType_NUM); i++) {
-            if (m_requestTypeVec[i] > 0) {
+            if (m_cacheRequestType[i] > 0) {
                 out << description << "_request_type_"
                     << CacheRequestType_to_string(CacheRequestType(i))
                     << ":   "
-                    << 100.0 * (double)m_requestTypeVec[i] /
+                    << 100.0 * (double)m_cacheRequestType[i] /
+                    (double)requests
+                    << "%" << endl;
+            }
+        }
+
+        for (int i = 0; i < int(GenericRequestType_NUM); i++) {
+            if (m_genericRequestType[i] > 0) {
+                out << description << "_request_type_"
+                    << GenericRequestType_to_string(GenericRequestType(i))
+                    << ":   "
+                    << 100.0 * (double)m_genericRequestType[i] /
                     (double)requests
                     << "%" << endl;
             }
@@ -90,7 +105,6 @@ CacheProfiler::printStats(ostream& out) const
         }
     }
 
-    out << description << "_request_size: " << m_requestSize << endl;
     out << endl;
 }
 
@@ -98,9 +112,11 @@ void
 CacheProfiler::clearStats()
 {
     for (int i = 0; i < int(CacheRequestType_NUM); i++) {
-        m_requestTypeVec[i] = 0;
+        m_cacheRequestType[i] = 0;
+    }
+    for (int i = 0; i < int(GenericRequestType_NUM); i++) {
+        m_genericRequestType[i] = 0;
     }
-    m_requestSize.clear();
     m_misses = 0;
     m_demand_misses = 0;
     m_prefetches = 0;
@@ -112,16 +128,30 @@ CacheProfiler::clearStats()
 }
 
 void
-CacheProfiler::addStatSample(CacheRequestType requestType,
-                             AccessModeType type, int msgSize,
+CacheProfiler::addCacheStatSample(CacheRequestType requestType,
+                                  AccessModeType accessType, 
+                                  PrefetchBit pfBit)
+{
+    m_cacheRequestType[requestType]++;
+    addStatSample(accessType, pfBit);
+}
+
+void
+CacheProfiler::addGenericStatSample(GenericRequestType requestType,
+                                    AccessModeType accessType, 
+                                    PrefetchBit pfBit)
+{
+    m_genericRequestType[requestType]++;
+    addStatSample(accessType, pfBit);
+}
+
+void
+CacheProfiler::addStatSample(AccessModeType accessType, 
                              PrefetchBit pfBit)
 {
     m_misses++;
 
-    m_requestTypeVec[requestType]++;
-
-    m_accessModeTypeHistogram[type]++;
-    m_requestSize.add(msgSize);
+    m_accessModeTypeHistogram[accessType]++;
     if (pfBit == PrefetchBit_No) {
         m_demand_misses++;
     } else if (pfBit == PrefetchBit_Yes) {
diff --git a/src/mem/ruby/profiler/CacheProfiler.hh b/src/mem/ruby/profiler/CacheProfiler.hh
index fad60711b..2e59c9d82 100644
--- a/src/mem/ruby/profiler/CacheProfiler.hh
+++ b/src/mem/ruby/profiler/CacheProfiler.hh
@@ -35,6 +35,7 @@
 
 #include "mem/protocol/AccessModeType.hh"
 #include "mem/protocol/CacheRequestType.hh"
+#include "mem/protocol/GenericRequestType.hh"
 #include "mem/protocol/PrefetchBit.hh"
 #include "mem/ruby/common/Global.hh"
 #include "mem/ruby/common/Histogram.hh"
@@ -49,8 +50,13 @@ class CacheProfiler
     void printStats(std::ostream& out) const;
     void clearStats();
 
-    void addStatSample(CacheRequestType requestType, AccessModeType type,
-                       int msgSize, PrefetchBit pfBit);
+    void addCacheStatSample(CacheRequestType requestType, 
+                            AccessModeType type,
+                            PrefetchBit pfBit);
+
+    void addGenericStatSample(GenericRequestType requestType, 
+                              AccessModeType type,
+                              PrefetchBit pfBit);
 
     void print(std::ostream& out) const;
 
@@ -58,9 +64,9 @@ class CacheProfiler
     // Private copy constructor and assignment operator
     CacheProfiler(const CacheProfiler& obj);
     CacheProfiler& operator=(const CacheProfiler& obj);
+    void addStatSample(AccessModeType type, PrefetchBit pfBit);
 
     std::string m_description;
-    Histogram m_requestSize;
     int64 m_misses;
     int64 m_demand_misses;
     int64 m_prefetches;
@@ -68,7 +74,8 @@ class CacheProfiler
     int64 m_hw_prefetches;
     int64 m_accessModeTypeHistogram[AccessModeType_NUM];
 
-    std::vector<int> m_requestTypeVec;
+    std::vector<int> m_cacheRequestType;
+    std::vector<int> m_genericRequestType;
 };
 
 inline std::ostream&