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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-14 19:28:42 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-14 19:28:42 -0500 |
| commit | 1a3e8a3370f7ed904c05eef4066d46052e028d3f (patch) | |
| tree | dd2e7ba24b84fd8c873e95050f26a3d99973efa2 /src/mem/ruby/slicc_interface/AbstractCacheEntry.hh | |
| parent | d383a08f16e5874bbebdb5ae88f95d3c5c6eb919 (diff) | |
| download | gem5-1a3e8a3370f7ed904c05eef4066d46052e028d3f.tar.xz | |
ruby: handle llsc accesses through CacheEntry, not CacheMemory
The sequencer takes care of llsc accesses by calling upon functions
from the CacheMemory. This is unnecessary once the required CacheEntry object
is available. Thus some of the calls to findTagInSet() are avoided.
Diffstat (limited to 'src/mem/ruby/slicc_interface/AbstractCacheEntry.hh')
| -rw-r--r-- | src/mem/ruby/slicc_interface/AbstractCacheEntry.hh | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh index 6c7a4a008..2b318957f 100644 --- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh +++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh @@ -56,6 +56,11 @@ class AbstractCacheEntry : public AbstractEntry virtual DataBlock& getDataBlk() { panic("getDataBlk() not implemented!"); } + // Functions for locking and unlocking the cache entry. These are required + // for supporting atomic memory accesses. + void setLocked(int context); + void clearLocked(); + bool isLocked(int context) const; Addr m_Address; // Address of this block, required by CacheMemory int m_locked; // Holds info whether the address is locked, |