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authorBrad Beckmann <Brad.Beckmann@amd.com>2011-02-23 16:41:59 -0800
committerBrad Beckmann <Brad.Beckmann@amd.com>2011-02-23 16:41:59 -0800
commit12a05c23b7d351afee4b0c531021d8fb8ea5f57d (patch)
tree99a18647ecf642166068187915f2816a1007567d /src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
parent7842e955193c3fba850201acc45001306fe2ff9b (diff)
downloadgem5-12a05c23b7d351afee4b0c531021d8fb8ea5f57d.tar.xz
ruby: automate permission setting
This patch integrates permissions with cache and memory states, and then automates the setting of permissions within the generated code. No longer does one need to manually set the permissions within the setState funciton. This patch will faciliate easier functional access support by always correctly setting permissions for both cache and memory states. --HG-- rename : src/mem/slicc/ast/EnumDeclAST.py => src/mem/slicc/ast/StateDeclAST.py rename : src/mem/slicc/ast/TypeFieldEnumAST.py => src/mem/slicc/ast/TypeFieldStateAST.py
Diffstat (limited to 'src/mem/ruby/slicc_interface/AbstractCacheEntry.hh')
-rw-r--r--src/mem/ruby/slicc_interface/AbstractCacheEntry.hh5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
index 87c96a9cb..69333f481 100644
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
@@ -48,15 +48,12 @@ class AbstractCacheEntry : public AbstractEntry
AbstractCacheEntry();
virtual ~AbstractCacheEntry() = 0;
- // Get/Set permission of cache entry
- AccessPermission getPermission() const;
+ // Get/Set permission of the entry
void changePermission(AccessPermission new_perm);
Address m_Address; // Address of this block, required by CacheMemory
Time m_LastRef; // Last time this block was referenced, required
// by CacheMemory
- AccessPermission m_Permission; // Access permission for this
- // block, required by CacheMemory
int m_locked; // Holds info whether the address is locked,
// required for implementing LL/SC
};