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authorNilay Vaish <nilay@cs.wisc.edu>2015-08-14 12:04:51 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-08-14 12:04:51 -0500
commit91a84c5b3cfb888794ac0245c066a4724b9a0871 (patch)
tree79a8b41aff56655dbd187934d2709fdd7488c6ed /src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
parent9ea5d9cad9381e05004de28ef25309ebe94c3a79 (diff)
downloadgem5-91a84c5b3cfb888794ac0245c066a4724b9a0871.tar.xz
ruby: replace Address by Addr
This patch eliminates the type Address defined by the ruby memory system. This memory system would now use the type Addr that is in use by the rest of the system.
Diffstat (limited to 'src/mem/ruby/slicc_interface/AbstractCacheEntry.hh')
-rw-r--r--src/mem/ruby/slicc_interface/AbstractCacheEntry.hh2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
index 2ba128493..6c7a4a008 100644
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
@@ -57,7 +57,7 @@ class AbstractCacheEntry : public AbstractEntry
{ panic("getDataBlk() not implemented!"); }
- Address m_Address; // Address of this block, required by CacheMemory
+ Addr m_Address; // Address of this block, required by CacheMemory
int m_locked; // Holds info whether the address is locked,
// required for implementing LL/SC
};