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author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-11-06 05:42:20 -0600 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-11-06 05:42:20 -0600 |
commit | d25b722e4a9500f2d4b2ca937900bf093242ddfa (patch) | |
tree | 8eaa415786c9f2ac2ffff67799068381fdbaf90f /src/mem/ruby/slicc_interface/AbstractCacheEntry.hh | |
parent | 0baaed60ab961b8eb3399ee2c34adeea7335f5b3 (diff) | |
download | gem5-d25b722e4a9500f2d4b2ca937900bf093242ddfa.tar.xz |
ruby: coherence protocols: remove data block from dirctory entry
This patch removes the data block present in the directory entry structure
of each protocol in gem5's mainline. Firstly, this is required for moving
towards common set of memory controllers for classic and ruby memory systems.
Secondly, the data block was being misused in several places. It was being
used for having free access to the physical memory instead of calling on the
memory controller.
From now on, the directory controller will not have a direct visibility into
the physical memory. The Memory Vector object now resides in the
Memory Controller class. This also means that some significant changes are
being made to the functional accesses in ruby.
Diffstat (limited to 'src/mem/ruby/slicc_interface/AbstractCacheEntry.hh')
-rw-r--r-- | src/mem/ruby/slicc_interface/AbstractCacheEntry.hh | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh index ff5ff25ab..2ba128493 100644 --- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh +++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh @@ -35,6 +35,7 @@ #include <iostream> +#include "base/misc.hh" #include "mem/protocol/AccessPermission.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/slicc_interface/AbstractEntry.hh" @@ -50,6 +51,12 @@ class AbstractCacheEntry : public AbstractEntry // Get/Set permission of the entry void changePermission(AccessPermission new_perm); + // The methods below are those called by ruby runtime, add when it + // is absolutely necessary and should all be virtual function. + virtual DataBlock& getDataBlk() + { panic("getDataBlk() not implemented!"); } + + Address m_Address; // Address of this block, required by CacheMemory int m_locked; // Holds info whether the address is locked, // required for implementing LL/SC |