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authorNilay Vaish <nilay@cs.wisc.edu>2015-08-14 12:04:51 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-08-14 12:04:51 -0500
commit91a84c5b3cfb888794ac0245c066a4724b9a0871 (patch)
tree79a8b41aff56655dbd187934d2709fdd7488c6ed /src/mem/ruby/slicc_interface/AbstractController.cc
parent9ea5d9cad9381e05004de28ef25309ebe94c3a79 (diff)
downloadgem5-91a84c5b3cfb888794ac0245c066a4724b9a0871.tar.xz
ruby: replace Address by Addr
This patch eliminates the type Address defined by the ruby memory system. This memory system would now use the type Addr that is in use by the rest of the system.
Diffstat (limited to 'src/mem/ruby/slicc_interface/AbstractController.cc')
-rw-r--r--src/mem/ruby/slicc_interface/AbstractController.cc29
1 files changed, 13 insertions, 16 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index 64d581359..9ed8b08d0 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -93,7 +93,7 @@ AbstractController::profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
}
void
-AbstractController::stallBuffer(MessageBuffer* buf, Address addr)
+AbstractController::stallBuffer(MessageBuffer* buf, Addr addr)
{
if (m_waiting_buffers.count(addr) == 0) {
MsgVecType* msgVec = new MsgVecType;
@@ -107,7 +107,7 @@ AbstractController::stallBuffer(MessageBuffer* buf, Address addr)
}
void
-AbstractController::wakeUpBuffers(Address addr)
+AbstractController::wakeUpBuffers(Addr addr)
{
if (m_waiting_buffers.count(addr) > 0) {
//
@@ -127,7 +127,7 @@ AbstractController::wakeUpBuffers(Address addr)
}
void
-AbstractController::wakeUpAllBuffers(Address addr)
+AbstractController::wakeUpAllBuffers(Addr addr)
{
if (m_waiting_buffers.count(addr) > 0) {
//
@@ -186,14 +186,14 @@ AbstractController::wakeUpAllBuffers()
}
void
-AbstractController::blockOnQueue(Address addr, MessageBuffer* port)
+AbstractController::blockOnQueue(Addr addr, MessageBuffer* port)
{
m_is_blocking = true;
m_block_map[addr] = port;
}
void
-AbstractController::unblock(Address addr)
+AbstractController::unblock(Addr addr)
{
m_block_map.erase(addr);
if (m_block_map.size() == 0) {
@@ -209,11 +209,10 @@ AbstractController::getMasterPort(const std::string &if_name,
}
void
-AbstractController::queueMemoryRead(const MachineID &id, Address addr,
+AbstractController::queueMemoryRead(const MachineID &id, Addr addr,
Cycles latency)
{
- RequestPtr req = new Request(addr.getAddress(),
- RubySystem::getBlockSizeBytes(), 0,
+ RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
m_masterId);
PacketPtr pkt = Packet::createRead(req);
@@ -234,11 +233,10 @@ AbstractController::queueMemoryRead(const MachineID &id, Address addr,
}
void
-AbstractController::queueMemoryWrite(const MachineID &id, Address addr,
+AbstractController::queueMemoryWrite(const MachineID &id, Addr addr,
Cycles latency, const DataBlock &block)
{
- RequestPtr req = new Request(addr.getAddress(),
- RubySystem::getBlockSizeBytes(), 0,
+ RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
m_masterId);
PacketPtr pkt = Packet::createWrite(req);
@@ -262,18 +260,17 @@ AbstractController::queueMemoryWrite(const MachineID &id, Address addr,
}
void
-AbstractController::queueMemoryWritePartial(const MachineID &id, Address addr,
+AbstractController::queueMemoryWritePartial(const MachineID &id, Addr addr,
Cycles latency,
const DataBlock &block, int size)
{
- RequestPtr req = new Request(addr.getAddress(),
- RubySystem::getBlockSizeBytes(), 0,
+ RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
m_masterId);
PacketPtr pkt = Packet::createWrite(req);
uint8_t *newData = new uint8_t[size];
pkt->dataDynamic(newData);
- memcpy(newData, block.getData(addr.getOffset(), size), size);
+ memcpy(newData, block.getData(getOffset(addr), size), size);
SenderState *s = new SenderState(id);
pkt->pushSenderState(s);
@@ -310,7 +307,7 @@ AbstractController::recvTimingResp(PacketPtr pkt)
assert(pkt->isResponse());
std::shared_ptr<MemoryMsg> msg = std::make_shared<MemoryMsg>(clockEdge());
- (*msg).m_addr.setAddress(pkt->getAddr());
+ (*msg).m_addr = pkt->getAddr();
(*msg).m_Sender = m_machineID;
SenderState *s = dynamic_cast<SenderState *>(pkt->senderState);