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authorNilay Vaish <nilay@cs.wisc.edu>2012-12-11 10:05:54 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2012-12-11 10:05:54 -0600
commit93e283abb348b81d086225f7861d94901c9b0888 (patch)
tree2f66e364c898392ac5538d1cb9726720c34eecfd /src/mem/ruby/slicc_interface/AbstractController.hh
parentd5023847951dcebcb38838cae0a141bd1a62e407 (diff)
downloadgem5-93e283abb348b81d086225f7861d94901c9b0888.tar.xz
ruby: add a prefetcher
This patch adds a prefetcher for the ruby memory system. The prefetcher is based on a prefetcher implemented by others (well, I don't know who wrote the original). The prefetcher does stride-based prefetching, both unit and non-unit. It obseves the misses in the cache and trains on these. After the training period is over, the prefetcher starts issuing prefetch requests to the controller.
Diffstat (limited to 'src/mem/ruby/slicc_interface/AbstractController.hh')
-rw-r--r--src/mem/ruby/slicc_interface/AbstractController.hh4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index c5cb46f1e..9ab924608 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -78,6 +78,10 @@ class AbstractController : public SimObject, public Consumer
//! The return value indicates the number of messages written with the
//! data from the packet.
virtual uint32_t functionalWriteBuffers(PacketPtr&) = 0;
+
+ //! Function for enqueuing a prefetch request
+ virtual void enqueuePrefetch(const Address&, const RubyRequestType&)
+ { fatal("Prefetches not implemented!");}
};
#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__