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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-03-13 18:19:08 +0000 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-06-13 15:52:32 +0000 |
| commit | 12db50c89584938839e035da47d206250cbfd7c2 (patch) | |
| tree | 831a4151b29cdc14958b8dab2cce97fc3136d7b6 /src/mem/ruby/slicc_interface/Controller.py | |
| parent | dd3fc1f996679f4cfd29f980d43a0652542e6d9b (diff) | |
| download | gem5-12db50c89584938839e035da47d206250cbfd7c2.tar.xz | |
ruby: Add support for address ranges in the directory
Previously the directory covered a flat address range that always
started from address 0. This change adds a vector of address ranges
with interleaving and hashing that each directory keeps track of and
the necessary flexibility to support systems with non continuous
memory ranges.
Change-Id: I6ea1c629bdf4c5137b7d9c89dbaf6c826adfd977
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2903
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/mem/ruby/slicc_interface/Controller.py')
| -rw-r--r-- | src/mem/ruby/slicc_interface/Controller.py | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py index ba7d17c7c..39a0ea912 100644 --- a/src/mem/ruby/slicc_interface/Controller.py +++ b/src/mem/ruby/slicc_interface/Controller.py @@ -1,3 +1,15 @@ +# Copyright (c) 2017 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2009 Advanced Micro Devices, Inc. # All rights reserved. # @@ -37,6 +49,8 @@ class RubyController(MemObject): cxx_header = "mem/ruby/slicc_interface/AbstractController.hh" abstract = True version = Param.Int("") + addr_ranges = VectorParam.AddrRange([AllMemory], "Address range this " + "controller responds to") cluster_id = Param.UInt32(0, "Id of this controller's cluster") transitions_per_cycle = \ |