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author | Derek Hower <drh5@cs.wisc.edu> | 2009-07-18 18:20:03 -0500 |
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committer | Derek Hower <drh5@cs.wisc.edu> | 2009-07-18 18:20:03 -0500 |
commit | 7cd2d8f687bd6909b92da5301a2d305f1fc33601 (patch) | |
tree | f72b072981915ec07b20d08f0d280292efe3f8d2 /src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh | |
parent | 4bd7fe4c53471e4aa404f4b5e1d2dad68e3514f6 (diff) | |
download | gem5-7cd2d8f687bd6909b92da5301a2d305f1fc33601.tar.xz |
ruby: removed all refs to old RubyConfig
Diffstat (limited to 'src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh')
-rw-r--r-- | src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh | 110 |
1 files changed, 1 insertions, 109 deletions
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh index 9ece7ae65..cd3cdbe48 100644 --- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh +++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh @@ -35,7 +35,6 @@ #define COMPONENTMAPPINGFNS_H #include "mem/ruby/common/Global.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/system/NodeID.hh" #include "mem/ruby/system/MachineID.hh" #include "mem/ruby/common/Address.hh" @@ -62,77 +61,6 @@ #define MACHINETYPE_L3CACHE_ENUM MachineType_NUM #endif -/* -#ifdef MACHINETYPE_PersistentArbiter -#define MACHINETYPE_PERSISTENTARBITER_ENUM MachineType_PersistentArbiter -#else -#define MACHINETYPE_PERSISTENTARBITER_ENUM MachineType_NUM -#endif -*/ -/* -inline MachineID map_Address_to_L2Cache(const Address & addr) -{ - int L2bank = 0; - MachineID mach = {MACHINETYPE_L2CACHE_ENUM, 0}; - L2bank = addr.bitSelect(RubySystem::getBlockSizeBits(), - RubySystem::getBlockSizeBits() + RubyConfig::getNumberOfCachesPerLevel(2)-1); - mach.num = L2bank; - return mach; -} - -// input parameter is the base ruby node of the L1 cache -// returns a value between 0 and total_L2_Caches_within_the_system -inline -MachineID map_L1CacheMachId_to_L2Cache(const Address& addr, MachineID L1CacheMachId) -{ - return map_Address_to_L2Cache(addr); - - int L2bank = 0; - MachineID mach = {MACHINETYPE_L2CACHE_ENUM, 0}; - - if (RubyConfig::L2CachePerChipBits() > 0) { - if (RubyConfig::getMAP_L2BANKS_TO_LOWEST_BITS()) { - L2bank = addr.bitSelect(RubySystem::getBlockSizeBits(), - RubySystem::getBlockSizeBits()+RubyConfig::L2CachePerChipBits()-1); - } else { - L2bank = addr.bitSelect(RubySystem::getBlockSizeBits()+RubyConfig::getL2_CACHE_NUM_SETS_BITS(), - RubySystem::getBlockSizeBits()+RubyConfig::getL2_CACHE_NUM_SETS_BITS()+RubyConfig::L2CachePerChipBits()-1); - } - } - - assert(L2bank < RubyConfig::numberOfL2CachePerChip()); - assert(L2bank >= 0); - - mach.num = RubyConfig::L1CacheNumToL2Base(L1CacheMachId.num)*RubyConfig::numberOfL2CachePerChip() // base # - + L2bank; // bank # - assert(mach.num < RubyConfig::numberOfL2Cache()); - return mach; - -} - - -// used to determine the correct L2 bank -// input parameter is the base ruby node of the L2 cache -// returns a value between 0 and total_L2_Caches_within_the_system - -inline -MachineID map_L2ChipId_to_L2Cache(const Address& addr, NodeID L2ChipId) -{ - return map_Address_to_L2Cache(addr); - - assert(L2ChipId < RubyConfig::numberOfChips()); - - int L2bank = 0; - MachineID mach = {MACHINETYPE_L2CACHE_ENUM, 0}; - L2bank = addr.bitSelect(RubySystem::getBlockSizeBits(), - RubySystem::getBlockSizeBits() + RubyConfig::numberOfCachesPerLevel(2)-1); - mach.num = L2bank; - return mach - -} - */ - - // used to determine the home directory // returns a value between 0 and total_directories_within_the_system inline @@ -157,29 +85,8 @@ MachineID map_Address_to_DMA(const Address & addr) return dma; } -/* -inline -NetDest getOtherLocalL1IDs(MachineID L1) -{ - int start = (L1.num / RubyConfig::numberOfProcsPerChip()) * RubyConfig::numberOfProcsPerChip(); - NetDest ret; - - assert(MACHINETYPE_L1CACHE_ENUM != MachineType_NUM); - - for (int i = start; i < (start + RubyConfig::numberOfProcsPerChip()); i++) { - if (i != L1.num) { - MachineID mach = { MACHINETYPE_L1CACHE_ENUM, i }; - ret.add( mach ); - } - } - - return ret; -} -*/ - extern inline NodeID machineIDToNodeID(MachineID machID) { - // return machID.num%RubyConfig::numberOfChips(); return machID.num; } @@ -193,22 +100,7 @@ extern inline NodeID L1CacheMachIDToProcessorNum(MachineID machID) assert(machID.type == MachineType_L1Cache); return machID.num; } -/* -extern inline NodeID L2CacheMachIDToChipID(MachineID machID) -{ - assert(machID.type == MACHINETYPE_L2CACHE_ENUM); - int L2bank = machID.num; - int banks_seen = 0; - for (int i=0;i<RubyConfig::getNumberOfChips();i++) { - for (int j=0;j<RubyConfig::getNumberOfCachesPerLevelPerChip(2,i);j++) { - if (banks_seen == L2bank) - return i; - banks_seen++; - } - } - assert(0); -} -*/ + extern inline MachineID getL1MachineID(NodeID L1RubyNode) { MachineID mach = {MACHINETYPE_L1CACHE_ENUM, L1RubyNode}; |