ruby: Add support for address ranges in the directory

Previously the directory covered a flat address range that always
started from address 0. This change adds a vector of address ranges
with interleaving and hashing that each directory keeps track of and
the necessary flexibility to support systems with non continuous
memory ranges.

Change-Id: I6ea1c629bdf4c5137b7d9c89dbaf6c826adfd977
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2903
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

4 files changed, 73 insertions, 44 deletions

diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index 19dca9028..0bc88eefa 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2011-2014 Mark D. Hill and David A. Wood
  * All rights reserved.
  *
@@ -43,7 +55,8 @@ AbstractController::AbstractController(const Params *p)
       m_number_of_TBEs(p->number_of_TBEs),
       m_transitions_per_cycle(p->transitions_per_cycle),
       m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency),
-      memoryPort(csprintf("%s.memory", name()), this, "")
+      memoryPort(csprintf("%s.memory", name()), this, ""),
+      addrRanges(p->addr_ranges.begin(), p->addr_ranges.end())
 {
     if (m_version == 0) {
         // Combine the statistics from all controllers
@@ -347,6 +360,14 @@ AbstractController::recvTimingResp(PacketPtr pkt)
     delete pkt;
 }
 
+MachineID
+AbstractController::mapAddressToMachine(Addr addr, MachineType mtype) const
+{
+    NodeID node = m_net_ptr->addressToNodeID(addr, mtype);
+    MachineID mach = {mtype, node};
+    return mach;
+}
+
 bool
 AbstractController::MemoryPort::recvTimingResp(PacketPtr pkt)
 {
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index e4562145f..354dc80aa 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2017 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2009-2014 Mark D. Hill and David A. Wood
  * All rights reserved.
  *
@@ -33,8 +45,12 @@
 #include <iostream>
 #include <string>
 
+#include "base/addr_range.hh"
 #include "base/callback.hh"
+#include "mem/mem_object.hh"
+#include "mem/packet.hh"
 #include "mem/protocol/AccessPermission.hh"
+#include "mem/qport.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Consumer.hh"
 #include "mem/ruby/common/DataBlock.hh"
@@ -42,10 +58,7 @@
 #include "mem/ruby/common/MachineID.hh"
 #include "mem/ruby/network/MessageBuffer.hh"
 #include "mem/ruby/system/CacheRecorder.hh"
-#include "mem/packet.hh"
-#include "mem/qport.hh"
 #include "params/RubyController.hh"
-#include "mem/mem_object.hh"
 
 class Network;
 class GPUCoalescer;
@@ -123,6 +136,8 @@ class AbstractController : public MemObject, public Consumer
                                  const DataBlock &block, int size);
     void recvTimingResp(PacketPtr pkt);
 
+    const AddrRangeList &getAddrRanges() const { return addrRanges; }
+
   public:
     MachineID getMachineID() const { return m_machineID; }
 
@@ -130,6 +145,21 @@ class AbstractController : public MemObject, public Consumer
     Stats::Histogram& getDelayVCHist(uint32_t index)
     { return *(m_delayVCHistogram[index]); }
 
+    /**
+     * Map an address to the correct MachineID
+     *
+     * This function querries the network for the NodeID of the
+     * destination for a given request using its address and the type
+     * of the destination. For example for a request with a given
+     * address to a directory it will return the MachineID of the
+     * authorative directory.
+     *
+     * @param the destination address
+     * @param the type of the destination
+     * @return the MachineID of the destination
+     */
+    MachineID mapAddressToMachine(Addr addr, MachineType mtype) const;
+
   protected:
     //! Profiles original cache requests including PUTs
     void profileRequest(const std::string &request);
@@ -223,6 +253,10 @@ class AbstractController : public MemObject, public Consumer
         SenderState(MachineID _id) : id(_id)
         {}
     };
+
+  private:
+    /** The address range to which the controller responds on the CPU side. */
+    const AddrRangeList addrRanges;
 };
 
 #endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py
index ba7d17c7c..39a0ea912 100644
--- a/src/mem/ruby/slicc_interface/Controller.py
+++ b/src/mem/ruby/slicc_interface/Controller.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2009 Advanced Micro Devices, Inc.
 # All rights reserved.
 #
@@ -37,6 +49,8 @@ class RubyController(MemObject):
     cxx_header = "mem/ruby/slicc_interface/AbstractController.hh"
     abstract = True
     version = Param.Int("")
+    addr_ranges = VectorParam.AddrRange([AllMemory], "Address range this "
+                                        "controller responds to")
     cluster_id = Param.UInt32(0, "Id of this controller's cluster")
 
     transitions_per_cycle = \
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
index cdedc2e14..dfc2c73fc 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
@@ -35,46 +35,6 @@
 #include "mem/ruby/common/NetDest.hh"
 #include "mem/ruby/structures/DirectoryMemory.hh"
 
-// used to determine the home directory
-// returns a value between 0 and total_directories_within_the_system
-inline NodeID
-map_Address_to_DirectoryNode(Addr addr)
-{
-    return DirectoryMemory::mapAddressToDirectoryVersion(addr);
-}
-
-inline NodeID
-map_Address_to_TCCdirNode(Addr addr)
-{
-    return DirectoryMemory::mapAddressToDirectoryVersion(addr);
-}
-
-// used to determine the home directory
-// returns a value between 0 and total_directories_within_the_system
-inline MachineID
-map_Address_to_Directory(Addr addr)
-{
-    MachineID mach =
-        {MachineType_Directory, map_Address_to_DirectoryNode(addr)};
-    return mach;
-}
-
-inline MachineID
-map_Address_to_RegionDir(Addr addr)
-{
-    MachineID mach = {MachineType_RegionDir,
-                      map_Address_to_DirectoryNode(addr)};
-    return mach;
-}
-
-inline MachineID
-map_Address_to_TCCdir(Addr addr)
-{
-    MachineID mach =
-        {MachineType_TCCdir, map_Address_to_TCCdirNode(addr)};
-    return mach;
-}
-
 inline NetDest
 broadcast(MachineType type)
 {