ruby: reverts to changeset: bf82f1f7b040

3 files changed, 10 insertions, 53 deletions

diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
index 416aea73b..01fd3f522 100644
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
@@ -28,9 +28,6 @@
 
 #include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
 
-#include "base/trace.hh"
-#include "debug/RubyCache.hh"
-
 AbstractCacheEntry::AbstractCacheEntry()
 {
     m_Permission = AccessPermission_NotPresent;
@@ -51,25 +48,3 @@ AbstractCacheEntry::changePermission(AccessPermission new_perm)
         m_locked = -1;
     }
 }
-
-void
-AbstractCacheEntry::setLocked(int context)
-{
-    DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", m_Address, context);
-    m_locked = context;
-}
-
-void
-AbstractCacheEntry::clearLocked()
-{
-    DPRINTF(RubyCache, "Clear Lock for addr: %x\n", m_Address);
-    m_locked = -1;
-}
-
-bool
-AbstractCacheEntry::isLocked(int context) const
-{
-    DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n",
-            m_Address, m_locked, context);
-    return m_locked == context;
-}
diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
index 926556781..6c7a4a008 100644
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
@@ -56,28 +56,10 @@ class AbstractCacheEntry : public AbstractEntry
     virtual DataBlock& getDataBlk()
     { panic("getDataBlk() not implemented!"); }
 
-    // Functions for locking and unlocking the cache entry.  These are required
-    // for supporting atomic memory accesses.
-    void setLocked(int context);
-    void clearLocked();
-    bool isLocked(int context) const;
 
-    void setSetIndex(uint32_t s) { m_set_index = s; }
-    uint32_t getSetIndex() const { return m_set_index; }
-
-    void setWayIndex(uint32_t s) { m_way_index = s; }
-    uint32_t getWayIndex() const { return m_way_index; }
-
-    // Address of this block, required by CacheMemory
-    Addr m_Address;
-    // Holds info whether the address is locked.
-    // Required for implementing LL/SC operations.
-    int m_locked;
-
-  private:
-    // Set and way coordinates of the entry within the cache memory object.
-    uint32_t m_set_index;
-    uint32_t m_way_index;
+    Addr m_Address; // Address of this block, required by CacheMemory
+    int m_locked; // Holds info whether the address is locked,
+                  // required for implementing LL/SC
 };
 
 inline std::ostream&
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index 34160c149..94361034a 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -139,14 +139,14 @@ class AbstractController : public MemObject, public Consumer
     void wakeUpAllBuffers();
 
   protected:
-    const NodeID m_version;
+    NodeID m_version;
     MachineID m_machineID;
-    const NodeID m_clusterID;
+    NodeID m_clusterID;
 
     // MasterID used by some components of gem5.
-    const MasterID m_masterId;
+    MasterID m_masterId;
 
-    Network *m_net_ptr;
+    Network* m_net_ptr;
     bool m_is_blocking;
     std::map<Addr, MessageBuffer*> m_block_map;
 
@@ -157,9 +157,9 @@ class AbstractController : public MemObject, public Consumer
 
     unsigned int m_in_ports;
     unsigned int m_cur_in_port;
-    const int m_number_of_TBEs;
-    const int m_transitions_per_cycle;
-    const unsigned int m_buffer_size;
+    int m_number_of_TBEs;
+    int m_transitions_per_cycle;
+    unsigned int m_buffer_size;
     Cycles m_recycle_latency;
 
     //! Counter for the number of cycles when the transitions carried out