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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-04-28 17:18:14 -0700 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-04-28 17:18:14 -0700 |
| commit | 40bcbf42539fec83628f2ae2627238adff27f62c (patch) | |
| tree | 993083e3b6e5661697261e81869bf40e17027826 /src/mem/ruby/slicc_interface | |
| parent | bc5eb596053f7f69c88f8218f20709d94b2a331c (diff) | |
| download | gem5-40bcbf42539fec83628f2ae2627238adff27f62c.tar.xz | |
network: convert links & switches to first class C++ SimObjects
This patch converts links and switches from second class simobjects that were
virtually ignored by the networks (both simple and Garnet) to first class
simobjects that directly correspond to c++ ojbects manipulated by the
topology and network classes. This is especially true for Garnet, where the
links and switches directly correspond to specific C++ objects.
By making this change, many aspects of the Topology class were simplified.
--HG--
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/BasicLink.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/BasicLink.hh
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py
rename : src/mem/ruby/network/Network.cc => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.cc
rename : src/mem/ruby/network/Network.hh => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py
rename : src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py => src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py
Diffstat (limited to 'src/mem/ruby/slicc_interface')
| -rw-r--r-- | src/mem/ruby/slicc_interface/AbstractController.hh | 1 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/Controller.py | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh index 44e47c8ca..fcfe104b3 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.hh +++ b/src/mem/ruby/slicc_interface/AbstractController.hh @@ -47,6 +47,7 @@ class AbstractController : public SimObject, public Consumer public: typedef RubyControllerParams Params; AbstractController(const Params *p) : SimObject(p) {} + const Params *params() const { return (const Params *)_params; } // returns the number of controllers created of the specific subtype // virtual int getNumberOfControllers() const = 0; diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py index dc65e7f7e..a5ad45145 100644 --- a/src/mem/ruby/slicc_interface/Controller.py +++ b/src/mem/ruby/slicc_interface/Controller.py @@ -35,6 +35,7 @@ class RubyController(SimObject): cxx_class = 'AbstractController' abstract = True version = Param.Int("") + cntrl_id = Param.Int("") transitions_per_cycle = \ Param.Int(32, "no. of SLICC state machine transitions per cycle") buffer_size = Param.Int(0, "max buffer size 0 means infinite") |