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authorSwapnil Haria <swapnilster@gmail.com>2017-11-09 13:04:39 -0600
committerSwapnil Haria <swapnilster@gmail.com>2017-12-15 00:50:32 +0000
commit6ab6c52b0bf9c91ef9249613cb4c9d8ab579b4f3 (patch)
tree8da65d170bf38e885eec878d7cb4fa934a81e3c7 /src/mem/ruby/slicc_interface
parentc5095c75f7a721551816efd16196d88eb997ec5a (diff)
downloadgem5-6ab6c52b0bf9c91ef9249613cb4c9d8ab579b4f3.tar.xz
mem-ruby: Support atomic_noncaching acceses in ruby
Ruby has no support for atomic_noncaching accesses, which prevents using it with kvm-cpu. This patch fixes this by directly forwarding atomic requests from the ruby port/sequencer to the corresponding directory based on the destination address of the packet. Change-Id: I0b4928bfda44fd9e5e48583c51d1ea422800da2d Reviewed-on: https://gem5-review.googlesource.com/5601 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Diffstat (limited to 'src/mem/ruby/slicc_interface')
-rw-r--r--src/mem/ruby/slicc_interface/AbstractController.cc6
-rw-r--r--src/mem/ruby/slicc_interface/AbstractController.hh1
2 files changed, 7 insertions, 0 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index 0bc88eefa..b920ff7b0 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -360,6 +360,12 @@ AbstractController::recvTimingResp(PacketPtr pkt)
delete pkt;
}
+Tick
+AbstractController::recvAtomic(PacketPtr pkt)
+{
+ return ticksToCycles(memoryPort.sendAtomic(pkt));
+}
+
MachineID
AbstractController::mapAddressToMachine(Addr addr, MachineType mtype) const
{
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index 354dc80aa..35cd3d2a5 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -135,6 +135,7 @@ class AbstractController : public MemObject, public Consumer
void queueMemoryWritePartial(const MachineID &id, Addr addr, Cycles latency,
const DataBlock &block, int size);
void recvTimingResp(PacketPtr pkt);
+ Tick recvAtomic(PacketPtr pkt);
const AddrRangeList &getAddrRanges() const { return addrRanges; }