ruby: automate permission setting

This patch integrates permissions with cache and memory states, and then
automates the setting of permissions within the generated code.  No longer
does one need to manually set the permissions within the setState funciton.
This patch will faciliate easier functional access support by always correctly
setting permissions for both cache and memory states.

--HG--
rename : src/mem/slicc/ast/EnumDeclAST.py => src/mem/slicc/ast/StateDeclAST.py
rename : src/mem/slicc/ast/TypeFieldEnumAST.py => src/mem/slicc/ast/TypeFieldStateAST.py

4 files changed, 23 insertions, 12 deletions

diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
index d53697c76..137a6c950 100644
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
@@ -30,8 +30,8 @@
 
 AbstractCacheEntry::AbstractCacheEntry()
 {
-    m_Address.setAddress(0);
     m_Permission = AccessPermission_NotPresent;
+    m_Address.setAddress(0);
     m_locked = -1;
 }
 
@@ -39,16 +39,10 @@ AbstractCacheEntry::~AbstractCacheEntry()
 {
 }
 
-AccessPermission
-AbstractCacheEntry::getPermission() const
-{
-    return m_Permission;
-}
-
 void
 AbstractCacheEntry::changePermission(AccessPermission new_perm)
 {
-    m_Permission = new_perm;
+    AbstractEntry::changePermission(new_perm);
     if ((new_perm == AccessPermission_Invalid) ||
         (new_perm == AccessPermission_NotPresent)) {
         m_locked = -1;
diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
index 87c96a9cb..69333f481 100644
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
@@ -48,15 +48,12 @@ class AbstractCacheEntry : public AbstractEntry
     AbstractCacheEntry();
     virtual ~AbstractCacheEntry() = 0;
 
-    // Get/Set permission of cache entry
-    AccessPermission getPermission() const;
+    // Get/Set permission of the entry
     void changePermission(AccessPermission new_perm);
 
     Address m_Address; // Address of this block, required by CacheMemory
     Time m_LastRef; // Last time this block was referenced, required
                     // by CacheMemory
-    AccessPermission m_Permission; // Access permission for this
-                                   // block, required by CacheMemory
     int m_locked; // Holds info whether the address is locked,
                   // required for implementing LL/SC
 };
diff --git a/src/mem/ruby/slicc_interface/AbstractEntry.cc b/src/mem/ruby/slicc_interface/AbstractEntry.cc
index d66258eef..51f16df6a 100644
--- a/src/mem/ruby/slicc_interface/AbstractEntry.cc
+++ b/src/mem/ruby/slicc_interface/AbstractEntry.cc
@@ -30,8 +30,21 @@
 
 AbstractEntry::AbstractEntry()
 {
+    m_Permission = AccessPermission_NotPresent;
 }
 
 AbstractEntry::~AbstractEntry()
 {
 }
+
+AccessPermission
+AbstractEntry::getPermission() const
+{
+    return m_Permission;
+}
+
+void
+AbstractEntry::changePermission(AccessPermission new_perm)
+{
+    m_Permission = new_perm;
+}
diff --git a/src/mem/ruby/slicc_interface/AbstractEntry.hh b/src/mem/ruby/slicc_interface/AbstractEntry.hh
index 19852fbe9..6752bf6c4 100644
--- a/src/mem/ruby/slicc_interface/AbstractEntry.hh
+++ b/src/mem/ruby/slicc_interface/AbstractEntry.hh
@@ -43,11 +43,18 @@ class AbstractEntry
     AbstractEntry();
     virtual ~AbstractEntry() = 0;
 
+    // Get/Set permission of the entry
+    AccessPermission getPermission() const;
+    void changePermission(AccessPermission new_perm);
+
     // The methods below are those called by ruby runtime, add when it
     // is absolutely necessary and should all be virtual function.
     virtual DataBlock& getDataBlk() = 0;
 
     virtual void print(std::ostream& out) const = 0;
+
+    AccessPermission m_Permission; // Access permission for this
+                                   // block, required by CacheMemory
 };
 
 inline std::ostream&