invisispec-1.0 source

3 files changed, 111 insertions, 2 deletions

diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index 5f7eb6558..d36885386 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -41,6 +41,7 @@
 #include "mem/ruby/slicc_interface/AbstractController.hh"
 
 #include "debug/RubyQueue.hh"
+#include "debug/MemSpecBuffer.hh"
 #include "mem/protocol/MemoryMsg.hh"
 #include "mem/ruby/network/Network.hh"
 #include "mem/ruby/system/GPUCoalescer.hh"
@@ -96,6 +97,14 @@ AbstractController::regStats()
         .name(name() + ".fully_busy_cycles")
         .desc("cycles for which number of transistions == max transitions")
         .flags(Stats::nozero);
+    m_expose_hits
+        .name(name() + ".expose_hits")
+        .desc("number of expose hits at LLC spec buffer")
+        .flags(Stats::nozero);
+    m_expose_misses
+        .name(name() + ".expose_misses")
+        .desc("number of expose misses at LLC spec buffer")
+        .flags(Stats::nozero);
 }
 
 void
@@ -238,8 +247,67 @@ AbstractController::getMasterPort(const std::string &if_name,
 
 void
 AbstractController::queueMemoryRead(const MachineID &id, Addr addr,
-                                    Cycles latency)
+                                    Cycles latency, MachineID origin, int idx, int type)
 {
+    int coreId = origin.num;
+    int sbeId = idx;
+    // type 0: non-spec 1: spec 2: expose
+    // DPRINTFR(MemSpecBuffer, "%10s MemRead (core=%d, type=%d, idx=%d, addr=%#x)\n", curTick(), coreId, type, sbeId, printAddress(addr));
+    // if idx == -1, it is a write request which cannot be spec or expose.
+    assert(!(type != 0 && sbeId == -1));
+    assert(sbeId >= -1 && sbeId <= 65);
+    assert(coreId < 8);
+    assert(type >=0 && type <= 2);
+    if (type == 0) {
+        for (int c = 0; c < 8; ++c) {
+            for (int i = 0; i < 66; ++i) {
+                if (m_specBuf[c][i].address == addr) {
+                    DPRINTFR(MemSpecBuffer, "%10s Cleared by Read (core=%d, type=%d, idx=%d, addr=%#x)\n", curTick(), c, type, i, printAddress(addr));
+                    m_specBuf[c][i].address = 0;
+                    m_specBuf[c][i].data.clear();
+                }
+            }
+        }
+    } else if (type == 1) {
+
+    } else if (type == 2) {
+        if (m_specBuf[coreId][sbeId].address == addr) {
+            DPRINTFR(MemSpecBuffer, "%10s Expose Hit (core=%d, type=%d, idx=%d, addr=%#x)\n", curTick(), coreId, type, sbeId, printAddress(addr));
+            ++m_expose_hits;
+            assert(getMemoryQueue());
+            std::shared_ptr<MemoryMsg> msg = std::make_shared<MemoryMsg>(clockEdge());
+            (*msg).m_addr = addr;
+            (*msg).m_Sender = m_machineID;
+            (*msg).m_OriginalRequestorMachId = id;
+            (*msg).m_Type = MemoryRequestType_MEMORY_READ;
+            (*msg).m_MessageSize = MessageSizeType_Response_Data;
+            (*msg).m_DataBlk = m_specBuf[coreId][sbeId].data;
+            getMemoryQueue()->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1)));
+            for (int c = 0; c < 8; ++c) {
+                for (int i = 0; i < 66; ++i) {
+                    if (m_specBuf[c][i].address == addr) {
+                        DPRINTFR(MemSpecBuffer, "%10s Cleared by Expose Hit (core=%d, type=%d, idx=%d, addr=%#x)\n", curTick(), c, type, i, printAddress(addr));
+                        m_specBuf[c][i].address = 0;
+                        m_specBuf[c][i].data.clear();
+                    }
+                }
+            }
+            return;
+        } else {
+            DPRINTFR(MemSpecBuffer, "%10s Expose Miss (core=%d, type=%d, idx=%d, addr=%#x)\n", curTick(), coreId, type, sbeId, printAddress(addr));
+            ++m_expose_misses;
+            for (int c = 0; c < 8; ++c) {
+                for (int i = 0; i < 66; ++i) {
+                    if (m_specBuf[c][i].address == addr) {
+                        DPRINTFR(MemSpecBuffer, "%10s Cleared by Expose Miss (core=%d, type=%d, idx=%d, addr=%#x)\n", curTick(), c, type, i, printAddress(addr));
+                        m_specBuf[c][i].address = 0;
+                        m_specBuf[c][i].data.clear();
+                    }
+                }
+            }
+        }
+    }
+    
     RequestPtr req = std::make_shared<Request>(
         addr, RubySystem::getBlockSizeBytes(), 0, m_masterId);
 
@@ -248,6 +316,9 @@ AbstractController::queueMemoryRead(const MachineID &id, Addr addr,
     pkt->dataDynamic(newData);
 
     SenderState *s = new SenderState(id);
+    s->type = type;
+    s->coreId = coreId;
+    s->sbeId = sbeId;
     pkt->pushSenderState(s);
 
     // Use functional rather than timing accesses during warmup
@@ -339,6 +410,9 @@ AbstractController::recvTimingResp(PacketPtr pkt)
 
     SenderState *s = dynamic_cast<SenderState *>(pkt->senderState);
     (*msg).m_OriginalRequestorMachId = s->id;
+    int type = s->type;
+    int coreId = s->coreId;
+    int sbeId = s->sbeId;
     delete s;
 
     if (pkt->isRead()) {
@@ -348,6 +422,12 @@ AbstractController::recvTimingResp(PacketPtr pkt)
         // Copy data from the packet
         (*msg).m_DataBlk.setData(pkt->getPtr<uint8_t>(), 0,
                                  RubySystem::getBlockSizeBytes());
+        if (type == 1) {
+            DPRINTFR(MemSpecBuffer, "%10s Updated by ReadSpec (core=%d, type=%d, idx=%d, addr=%#x)\n", curTick(), coreId, type, sbeId, printAddress(pkt->getAddr()));
+            m_specBuf[coreId][sbeId].address = pkt->getAddr();
+            m_specBuf[coreId][sbeId].data.setData(pkt->getPtr<uint8_t>(), 0,
+                                                  RubySystem::getBlockSizeBytes());
+        }
     } else if (pkt->isWrite()) {
         (*msg).m_Type = MemoryRequestType_MEMORY_WB;
         (*msg).m_MessageSize = MessageSizeType_Writeback_Control;
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index 35cd3d2a5..b65a511d0 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -129,7 +129,7 @@ class AbstractController : public MemObject, public Consumer
     BaseMasterPort& getMasterPort(const std::string& if_name,
                                   PortID idx = InvalidPortID);
 
-    void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency);
+    void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency, MachineID origin, int idx, int type);
     void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency,
                           const DataBlock &block);
     void queueMemoryWritePartial(const MachineID &id, Addr addr, Cycles latency,
@@ -199,6 +199,8 @@ class AbstractController : public MemObject, public Consumer
     //! Counter for the number of cycles when the transitions carried out
     //! were equal to the maximum allowed
     Stats::Scalar m_fully_busy_cycles;
+    Stats::Scalar m_expose_hits;
+    Stats::Scalar m_expose_misses;
 
     //! Histogram for profiling delay for the messages this controller
     //! cares for
@@ -250,6 +252,9 @@ class AbstractController : public MemObject, public Consumer
     {
         // Id of the machine from which the request originated.
         MachineID id;
+        int type;
+        int coreId;
+        int sbeId;
 
         SenderState(MachineID _id) : id(_id)
         {}
@@ -258,6 +263,14 @@ class AbstractController : public MemObject, public Consumer
   private:
     /** The address range to which the controller responds on the CPU side. */
     const AddrRangeList addrRanges;
+
+    struct SBE
+    {
+      Addr address;
+      DataBlock data;
+    };
+
+    SBE m_specBuf[8][66];
 };
 
 #endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
diff --git a/src/mem/ruby/slicc_interface/RubyRequest.hh b/src/mem/ruby/slicc_interface/RubyRequest.hh
index 6c84f3823..2fc4c9f98 100644
--- a/src/mem/ruby/slicc_interface/RubyRequest.hh
+++ b/src/mem/ruby/slicc_interface/RubyRequest.hh
@@ -60,6 +60,7 @@ class RubyRequest : public Message
     int m_wfid;
     HSAScope m_scope;
     HSASegment m_segment;
+    int m_idx;
 
 
     RubyRequest(Tick curTime, uint64_t _paddr, uint8_t* _data, int _len,
@@ -82,6 +83,11 @@ class RubyRequest : public Message
           m_segment(_segment)
     {
         m_LineAddress = makeLineAddress(m_PhysicalAddress);
+        if (_pkt->reqIdx == -1) {
+            m_idx = _pkt->reqIdx;
+        } else {
+            m_idx = (_pkt->reqIdx) * 2 + (_pkt->isFirst()? 0 : 1);
+        }
     }
 
     RubyRequest(Tick curTime, uint64_t _paddr, uint8_t* _data, int _len,
@@ -109,6 +115,11 @@ class RubyRequest : public Message
           m_segment(_segment)
     {
         m_LineAddress = makeLineAddress(m_PhysicalAddress);
+        if (_pkt->reqIdx == -1) {
+            m_idx = _pkt->reqIdx;
+        } else {
+            m_idx = (_pkt->reqIdx) * 2 + (_pkt->isFirst()? 0 : 1);
+        }
     }
 
     RubyRequest(Tick curTime, uint64_t _paddr, uint8_t* _data, int _len,
@@ -137,6 +148,11 @@ class RubyRequest : public Message
           m_segment(_segment)
     {
         m_LineAddress = makeLineAddress(m_PhysicalAddress);
+        if (_pkt->reqIdx == -1) {
+            m_idx = _pkt->reqIdx;
+        } else {
+            m_idx = (_pkt->reqIdx) * 2 + (_pkt->isFirst()? 0 : 1);
+        }
     }