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author | Joel Hestness <jthestness@gmail.com> | 2016-04-15 12:34:02 -0500 |
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committer | Joel Hestness <jthestness@gmail.com> | 2016-04-15 12:34:02 -0500 |
commit | 39e10ced035a7e1f53673fc998741f8b6067135d (patch) | |
tree | 481fd83c90f869034215115504d8eb5128e9a384 /src/mem/ruby/slicc_interface | |
parent | edbf748181bdd3ac86838e7c55d98a336b285e01 (diff) | |
download | gem5-39e10ced035a7e1f53673fc998741f8b6067135d.tar.xz |
ruby: Fix block_on behavior
Ruby's controller block_on behavior aimed to block MessageBuffer requests into
SLICC controllers when a Locked_RMW was in flight. Unfortunately, this
functionality only partially works: When non-Locked_RMW memory accesses are
issued to the sequencer to an address with an in-flight Locked_RMW, the
sequencer may pass those accesses through to the controller. At the controller,
a number of incorrect activities can occur depending on the protocol. In
MOESI_hammer, for example, an intermediate IFETCH will cause an L1D to L2
transfer, which cannot be serviced, because the block_on functionality blocks
the trigger queue, resulting in a deadlock. Further, if an intermediate store
arrives (e.g. from a separate SMT thread), the sequencer allows the request
through to the controller, and the atomicity of the Locked_RMW may be broken.
To avoid these problems, disallow the Sequencer from passing any memory
accesses to the controller besides Locked_RMW_Write when a Locked_RMW is in-
flight.
Diffstat (limited to 'src/mem/ruby/slicc_interface')
-rw-r--r-- | src/mem/ruby/slicc_interface/AbstractController.cc | 6 | ||||
-rw-r--r-- | src/mem/ruby/slicc_interface/AbstractController.hh | 1 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc index 2a53e53be..5d8b6eeea 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.cc +++ b/src/mem/ruby/slicc_interface/AbstractController.cc @@ -192,6 +192,12 @@ AbstractController::blockOnQueue(Addr addr, MessageBuffer* port) m_block_map[addr] = port; } +bool +AbstractController::isBlocked(Addr addr) const +{ + return m_is_blocking && (m_block_map.find(addr) != m_block_map.end()); +} + void AbstractController::unblock(Addr addr) { diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh index cfd11b8eb..6f49e5ec4 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.hh +++ b/src/mem/ruby/slicc_interface/AbstractController.hh @@ -73,6 +73,7 @@ class AbstractController : public MemObject, public Consumer // return instance name void blockOnQueue(Addr, MessageBuffer*); + bool isBlocked(Addr) const; void unblock(Addr); bool isBlocked(Addr); |