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| author | Akash Bagdia <akash.bagdia@ARM.com> | 2014-11-18 14:00:48 +0000 |
|---|---|---|
| committer | Akash Bagdia <akash.bagdia@ARM.com> | 2014-11-18 14:00:48 +0000 |
| commit | 3ee4957b4930a252c0185a6bc71bdf1c6ebc5ed9 (patch) | |
| tree | 6a7e1807397f002f51fddb34568b89250fca45c8 /src/mem/ruby/slicc_interface | |
| parent | 65ecd954861aa76532ca79453afcf66a837e1fa6 (diff) | |
| download | gem5-3ee4957b4930a252c0185a6bc71bdf1c6ebc5ed9.tar.xz | |
power: Add power states to ClockedObject
Add 4 power states to the ClockedObject, provides necessary access functions
to check and update the power state. Default power state is UNDEFINED, it is
responsibility of the respective simulation model to provide the startup state
and any other logic for state change.
Add number of transition stat.
Add distribution of time spent in clock gated state.
Add power state residency stat.
Add dump call back function to allow stats update of distribution and residency
stats.
Diffstat (limited to 'src/mem/ruby/slicc_interface')
| -rw-r--r-- | src/mem/ruby/slicc_interface/AbstractController.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc index 2a53e53be..be48628e9 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.cc +++ b/src/mem/ruby/slicc_interface/AbstractController.cc @@ -76,6 +76,8 @@ AbstractController::resetStats() void AbstractController::regStats() { + MemObject::regStats(); + m_fully_busy_cycles .name(name() + ".fully_busy_cycles") .desc("cycles for which number of transistions == max transitions") |