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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-01-11 13:29:15 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-01-11 13:29:15 -0600 |
| commit | c3109f77757b08f74768d44983ff81d7d66819e7 (patch) | |
| tree | 3aece55c468b05e7115b4b03c481dcc6be47bfad /src/mem/ruby/slicc_interface | |
| parent | ab0347a1c66da6d491b127ec1aeb193f35f73019 (diff) | |
| download | gem5-c3109f77757b08f74768d44983ff81d7d66819e7.tar.xz | |
Ruby: Add infrastructure for recording cache contents
This patch changes CacheRecorder, CacheMemory, CacheControllers
so that the contents of a cache can be recorded for checkpointing
purposes.
Diffstat (limited to 'src/mem/ruby/slicc_interface')
| -rw-r--r-- | src/mem/ruby/slicc_interface/AbstractController.hh | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh index ca37a90de..a0e3b3fbb 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.hh +++ b/src/mem/ruby/slicc_interface/AbstractController.hh @@ -33,12 +33,11 @@ #include <string> #include "mem/protocol/AccessPermission.hh" -#include "mem/protocol/MachineType.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/Consumer.hh" #include "mem/ruby/common/DataBlock.hh" #include "mem/ruby/network/Network.hh" -#include "mem/ruby/system/System.hh" +#include "mem/ruby/recorder/CacheRecorder.hh" #include "params/RubyController.hh" #include "sim/sim_object.hh" @@ -68,6 +67,8 @@ class AbstractController : public SimObject, public Consumer virtual void wakeup() = 0; // virtual void dumpStats(std::ostream & out) = 0; virtual void clearStats() = 0; + virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0; + virtual Sequencer* getSequencer() const = 0; }; #endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ |