diff options
| author | Gabe Black <gabeblack@google.com> | 2019-04-22 19:45:10 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-04-28 01:19:40 +0000 |
| commit | cdcc55a6a8fe9b4625b316a8d8845366ccfa71c9 (patch) | |
| tree | 893cea35432466600b55a2e4434ed61ba1e28f69 /src/mem/ruby/slicc_interface | |
| parent | 3cfff8574a19536e2b3d057b43b59fcf35932c81 (diff) | |
| download | gem5-cdcc55a6a8fe9b4625b316a8d8845366ccfa71c9.tar.xz | |
mem: Minimize the use of MemObject.
MemObject doesn't provide anything beyond its base ClockedObject any
more, so this change removes it from most inheritance hierarchies.
Occasionally MemObject is replaced with SimObject when I was fairly
confident that the extra functionality of ClockedObject wasn't needed.
Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/mem/ruby/slicc_interface')
| -rw-r--r-- | src/mem/ruby/slicc_interface/AbstractController.cc | 4 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/AbstractController.hh | 4 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/Controller.py | 4 |
3 files changed, 6 insertions, 6 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc index fa1c936b7..68edcba59 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.cc +++ b/src/mem/ruby/slicc_interface/AbstractController.cc @@ -49,7 +49,7 @@ #include "sim/system.hh" AbstractController::AbstractController(const Params *p) - : MemObject(p), Consumer(this), m_version(p->version), + : ClockedObject(p), Consumer(this), m_version(p->version), m_clusterID(p->cluster_id), m_masterId(p->system->getMasterId(this)), m_is_blocking(false), m_number_of_TBEs(p->number_of_TBEs), @@ -90,7 +90,7 @@ AbstractController::resetStats() void AbstractController::regStats() { - MemObject::regStats(); + ClockedObject::regStats(); m_fully_busy_cycles .name(name() + ".fully_busy_cycles") diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh index 5e39a28d2..4d0654698 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.hh +++ b/src/mem/ruby/slicc_interface/AbstractController.hh @@ -47,7 +47,6 @@ #include "base/addr_range.hh" #include "base/callback.hh" -#include "mem/mem_object.hh" #include "mem/packet.hh" #include "mem/protocol/AccessPermission.hh" #include "mem/qport.hh" @@ -59,6 +58,7 @@ #include "mem/ruby/network/MessageBuffer.hh" #include "mem/ruby/system/CacheRecorder.hh" #include "params/RubyController.hh" +#include "sim/clocked_object.hh" class Network; class GPUCoalescer; @@ -70,7 +70,7 @@ class RejectException: public std::exception { return "Port rejected message based on type"; } }; -class AbstractController : public MemObject, public Consumer +class AbstractController : public ClockedObject, public Consumer { public: typedef RubyControllerParams Params; diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py index 0eb704916..4d3c1900e 100644 --- a/src/mem/ruby/slicc_interface/Controller.py +++ b/src/mem/ruby/slicc_interface/Controller.py @@ -41,9 +41,9 @@ from m5.params import * from m5.proxy import * -from m5.objects.MemObject import MemObject +from m5.objects.ClockedObject import ClockedObject -class RubyController(MemObject): +class RubyController(ClockedObject): type = 'RubyController' cxx_class = 'AbstractController' cxx_header = "mem/ruby/slicc_interface/AbstractController.hh" |