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| author | David Hashe <david.hashe@amd.com> | 2015-07-20 09:15:18 -0500 |
|---|---|---|
| committer | David Hashe <david.hashe@amd.com> | 2015-07-20 09:15:18 -0500 |
| commit | 74ca89f8b7d9b340d1d4f83511b57a2dfa2a70df (patch) | |
| tree | d5763275304cbe0d6c662130a14b9459b29d5936 /src/mem/ruby/structures/BankedArray.hh | |
| parent | 536e3664e41d406af1e618dd02c3222f7cbbcaee (diff) | |
| download | gem5-74ca89f8b7d9b340d1d4f83511b57a2dfa2a70df.tar.xz | |
ruby: give access to cache tag/data latencies from SLICC
This patch exposes the tag and data array latencies to the SLICC state machines
so that it can be used to determine the correct enqueue latency for response
messages.
Diffstat (limited to 'src/mem/ruby/structures/BankedArray.hh')
| -rw-r--r-- | src/mem/ruby/structures/BankedArray.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/ruby/structures/BankedArray.hh b/src/mem/ruby/structures/BankedArray.hh index 5cc3eee32..dbfee9994 100644 --- a/src/mem/ruby/structures/BankedArray.hh +++ b/src/mem/ruby/structures/BankedArray.hh @@ -70,6 +70,7 @@ class BankedArray // This is so we don't get aliasing on blocks being replaced bool tryAccess(int64 idx); + Cycles getLatency() const { return accessLatency; } }; #endif |