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author | David Hashe <david.hashe@amd.com> | 2015-07-20 09:15:18 -0500 |
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committer | David Hashe <david.hashe@amd.com> | 2015-07-20 09:15:18 -0500 |
commit | 7e00772bda1a1c74fe659c56fea803642302c1da (patch) | |
tree | ade42a4e4b4bf3099c3c580045b3f9eaad8d789b /src/mem/ruby/structures/CacheMemory.cc | |
parent | 3454a4a36e927f483b36fa66baabe2c85ecf3ddc (diff) | |
download | gem5-7e00772bda1a1c74fe659c56fea803642302c1da.tar.xz |
ruby: speed up function used for cache walks
This patch adds a few helpful functions that allow .sm files to directly
invalidate all cache blocks using a trigger queue rather than rely on each
individual cache block to be invalidated via requests from the mandatory
queue.
Diffstat (limited to 'src/mem/ruby/structures/CacheMemory.cc')
-rw-r--r-- | src/mem/ruby/structures/CacheMemory.cc | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc index 047c024c9..486b5ae97 100644 --- a/src/mem/ruby/structures/CacheMemory.cc +++ b/src/mem/ruby/structures/CacheMemory.cc @@ -1,5 +1,6 @@ /* * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -134,6 +135,29 @@ CacheMemory::findTagInSetIgnorePermissions(int64 cacheSet, return -1; // Not found } +// Given an unique cache block identifier (idx): return the valid address +// stored by the cache block. If the block is invalid/notpresent, the +// function returns the 0 address +Address +CacheMemory::getAddressAtIdx(int idx) const +{ + Address tmp(0); + + int set = idx / m_cache_assoc; + assert(set < m_cache_num_sets); + + int way = idx - set * m_cache_assoc; + assert (way < m_cache_assoc); + + AbstractCacheEntry* entry = m_cache[set][way]; + if (entry == NULL || + entry->m_Permission == AccessPermission_Invalid || + entry->m_Permission == AccessPermission_NotPresent) { + return tmp; + } + return entry->m_Address; +} + bool CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type, DataBlock*& data_ptr) |