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| author | David Hashe <david.hashe@amd.com> | 2015-07-20 09:15:18 -0500 |
|---|---|---|
| committer | David Hashe <david.hashe@amd.com> | 2015-07-20 09:15:18 -0500 |
| commit | 74ca89f8b7d9b340d1d4f83511b57a2dfa2a70df (patch) | |
| tree | d5763275304cbe0d6c662130a14b9459b29d5936 /src/mem/ruby/structures/CacheMemory.hh | |
| parent | 536e3664e41d406af1e618dd02c3222f7cbbcaee (diff) | |
| download | gem5-74ca89f8b7d9b340d1d4f83511b57a2dfa2a70df.tar.xz | |
ruby: give access to cache tag/data latencies from SLICC
This patch exposes the tag and data array latencies to the SLICC state machines
so that it can be used to determine the correct enqueue latency for response
messages.
Diffstat (limited to 'src/mem/ruby/structures/CacheMemory.hh')
| -rw-r--r-- | src/mem/ruby/structures/CacheMemory.hh | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh index 4724da2b8..647520566 100644 --- a/src/mem/ruby/structures/CacheMemory.hh +++ b/src/mem/ruby/structures/CacheMemory.hh @@ -91,6 +91,9 @@ class CacheMemory : public SimObject const AbstractCacheEntry* lookup(const Address& address) const; Cycles getLatency() const { return m_latency; } + Cycles getTagLatency() const { return tagArray.getLatency(); } + Cycles getDataLatency() const { return dataArray.getLatency(); } + // Hook for checkpointing the contents of the cache void recordCacheContents(int cntrl, CacheRecorder* tr) const; |