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authorNilay Vaish <nilay@cs.wisc.edu>2015-08-14 19:28:43 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-08-14 19:28:43 -0500
commita706b6259a3cab71700078c4e2b91860cc2219c0 (patch)
tree19191bbcb0f466e17b7cf56c0cb569689cb2647a /src/mem/ruby/structures/CacheMemory.hh
parent5060e572ca07b98f7d84679bac81c0151dee46b9 (diff)
downloadgem5-a706b6259a3cab71700078c4e2b91860cc2219c0.tar.xz
ruby: cache memory: drop {try,test}CacheAccess functions
Diffstat (limited to 'src/mem/ruby/structures/CacheMemory.hh')
-rw-r--r--src/mem/ruby/structures/CacheMemory.hh9
1 files changed, 0 insertions, 9 deletions
diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh
index 7ce674e61..94174b286 100644
--- a/src/mem/ruby/structures/CacheMemory.hh
+++ b/src/mem/ruby/structures/CacheMemory.hh
@@ -56,15 +56,6 @@ class CacheMemory : public SimObject
void init();
- // Public Methods
- // perform a cache access and see if we hit or not. Return true on a hit.
- bool tryCacheAccess(Addr address, RubyRequestType type,
- DataBlock*& data_ptr);
-
- // similar to above, but doesn't require full access check
- bool testCacheAccess(Addr address, RubyRequestType type,
- DataBlock*& data_ptr);
-
// tests to see if an address is present in the cache
bool isTagPresent(Addr address) const;