summaryrefslogtreecommitdiff
path: root/src/mem/ruby/structures/CacheMemory.hh
diff options
context:
space:
mode:
authorNilay Vaish <nilay@cs.wisc.edu>2015-08-27 12:51:40 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-08-27 12:51:40 -0500
commitfc3d34a4889f96395d7d3185a0c5a2dbb5c77343 (patch)
tree2b5eccd49fab300132e4e4ccf0796cb437295a8e /src/mem/ruby/structures/CacheMemory.hh
parent88b1fd82a6207c38845c3503ab3037ed40225d80 (diff)
downloadgem5-fc3d34a4889f96395d7d3185a0c5a2dbb5c77343.tar.xz
ruby: handle llsc accesses through CacheEntry, not CacheMemory
The sequencer takes care of llsc accesses by calling upon functions from the CacheMemory. This is unnecessary once the required CacheEntry object is available. Thus some of the calls to findTagInSet() are avoided.
Diffstat (limited to 'src/mem/ruby/structures/CacheMemory.hh')
-rw-r--r--src/mem/ruby/structures/CacheMemory.hh5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh
index 08551ab87..6c719cb4f 100644
--- a/src/mem/ruby/structures/CacheMemory.hh
+++ b/src/mem/ruby/structures/CacheMemory.hh
@@ -107,6 +107,11 @@ class CacheMemory : public SimObject
// Set this address to most recently used
void setMRU(Addr address);
+ // Functions for locking and unlocking cache lines corresponding to the
+ // provided address. These are required for supporting atomic memory
+ // accesses. These are to be used when only the address of the cache entry
+ // is available. In case the entry itself is available. use the functions
+ // provided by the AbstractCacheEntry class.
void setLocked (Addr addr, int context);
void clearLocked (Addr addr);
bool isLocked (Addr addr, int context);