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author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-19 10:02:01 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-19 10:02:01 -0500 |
commit | 2f44dada688ace9c24f085a8422b3054c3edb72e (patch) | |
tree | 372bb043430552b0f4424eaa5571933883fcaaae /src/mem/ruby/structures/CacheMemory.hh | |
parent | 2d9f3f8582e2de60850852c803a8c8ba0d6b91b5 (diff) | |
download | gem5-2f44dada688ace9c24f085a8422b3054c3edb72e.tar.xz |
ruby: reverts to changeset: bf82f1f7b040
Diffstat (limited to 'src/mem/ruby/structures/CacheMemory.hh')
-rw-r--r-- | src/mem/ruby/structures/CacheMemory.hh | 28 |
1 files changed, 15 insertions, 13 deletions
diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh index 94174b286..08551ab87 100644 --- a/src/mem/ruby/structures/CacheMemory.hh +++ b/src/mem/ruby/structures/CacheMemory.hh @@ -56,6 +56,15 @@ class CacheMemory : public SimObject void init(); + // Public Methods + // perform a cache access and see if we hit or not. Return true on a hit. + bool tryCacheAccess(Addr address, RubyRequestType type, + DataBlock*& data_ptr); + + // similar to above, but doesn't require full access check + bool testCacheAccess(Addr address, RubyRequestType type, + DataBlock*& data_ptr); + // tests to see if an address is present in the cache bool isTagPresent(Addr address) const; @@ -89,22 +98,15 @@ class CacheMemory : public SimObject Cycles getTagLatency() const { return tagArray.getLatency(); } Cycles getDataLatency() const { return dataArray.getLatency(); } - bool isBlockInvalid(int64_t cache_set, int64_t loc); - bool isBlockNotBusy(int64_t cache_set, int64_t loc); + bool isBlockInvalid(int64 cache_set, int64 loc); + bool isBlockNotBusy(int64 cache_set, int64 loc); // Hook for checkpointing the contents of the cache void recordCacheContents(int cntrl, CacheRecorder* tr) const; // Set this address to most recently used void setMRU(Addr address); - // Set this entry to most recently used - void setMRU(const AbstractCacheEntry *e); - - // Functions for locking and unlocking cache lines corresponding to the - // provided address. These are required for supporting atomic memory - // accesses. These are to be used when only the address of the cache entry - // is available. In case the entry itself is available. use the functions - // provided by the AbstractCacheEntry class. + void setLocked (Addr addr, int context); void clearLocked (Addr addr); bool isLocked (Addr addr, int context); @@ -142,12 +144,12 @@ class CacheMemory : public SimObject private: // convert a Address to its location in the cache - int64_t addressToCacheSet(Addr address) const; + int64 addressToCacheSet(Addr address) const; // Given a cache tag: returns the index of the tag in a set. // returns -1 if the tag is not found. - int findTagInSet(int64_t line, Addr tag) const; - int findTagInSetIgnorePermissions(int64_t cacheSet, Addr tag) const; + int findTagInSet(int64 line, Addr tag) const; + int findTagInSetIgnorePermissions(int64 cacheSet, Addr tag) const; // Private copy constructor and assignment operator CacheMemory(const CacheMemory& obj); |