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authorAndreas Hansson <andreas.hansson@arm.com>2014-10-16 05:49:43 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2014-10-16 05:49:43 -0400
commitdf973abef3a70074971375cfe52c46f53528c00e (patch)
tree7c10603edb5c66631288cb0f9fa334df4cf3d8a9 /src/mem/ruby/structures/Prefetcher.hh
parent37908d62a4b45962a6e6f5993027b6b9bafa296d (diff)
downloadgem5-df973abef3a70074971375cfe52c46f53528c00e.tar.xz
mem: Dynamically determine page bytes in memory components
This patch takes a step towards an ISA-agnostic memory system by enabling the components to establish the page size after instantiation. The swap operation in the memory is now also allowing any granularity to avoid depending on the IntReg of the ISA.
Diffstat (limited to 'src/mem/ruby/structures/Prefetcher.hh')
-rw-r--r--src/mem/ruby/structures/Prefetcher.hh6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mem/ruby/structures/Prefetcher.hh b/src/mem/ruby/structures/Prefetcher.hh
index 2bc7d812e..6ed945b9e 100644
--- a/src/mem/ruby/structures/Prefetcher.hh
+++ b/src/mem/ruby/structures/Prefetcher.hh
@@ -41,6 +41,7 @@
#include "mem/ruby/system/System.hh"
#include "params/Prefetcher.hh"
#include "sim/sim_object.hh"
+#include "sim/system.hh"
#define MAX_PF_INFLIGHT 8
@@ -139,6 +140,9 @@ class Prefetcher : public SimObject
bool accessNonunitFilter(const Address& address, int *stride,
bool &alloc);
+ /// determine the page aligned address
+ Address pageAddress(const Address& addr) const;
+
//! number of prefetch streams available
uint32_t m_num_streams;
//! an array of the active prefetch streams
@@ -187,6 +191,8 @@ class Prefetcher : public SimObject
AbstractController *m_controller;
+ const Addr m_page_shift;
+
//! Count of accesses to the prefetcher
Stats::Scalar numMissObserved;
//! Count of prefetch streams allocated