ruby: interface with classic memory controller

This patch is the final in the series.  The whole series and this patch in
particular were written with the aim of interfacing ruby's directory controller
with the memory controller in the classic memory system.  This is being done
since ruby's memory controller has not being kept up to date with the changes
going on in DRAMs.  Classic's memory controller is more up to date and
supports multiple different types of DRAM.  This also brings classic and
ruby ever more close.  The patch also changes ruby's memory controller to
expose the same interface.

1 files changed, 6 insertions, 4 deletions

diff --git a/src/mem/ruby/structures/RubyMemoryControl.py b/src/mem/ruby/structures/RubyMemoryControl.py
index f0828fb19..78f2d8dcb 100644
--- a/src/mem/ruby/structures/RubyMemoryControl.py
+++ b/src/mem/ruby/structures/RubyMemoryControl.py
@@ -28,14 +28,12 @@
 #          Brad Beckmann
 
 from m5.params import *
-from m5.SimObject import SimObject
-from MemoryControl import MemoryControl
+from AbstractMemory import AbstractMemory
 
-class RubyMemoryControl(MemoryControl):
+class RubyMemoryControl(AbstractMemory):
     type = 'RubyMemoryControl'
     cxx_class = 'RubyMemoryControl'
     cxx_header = "mem/ruby/structures/RubyMemoryControl.hh"
-    version = Param.Int("");
 
     banks_per_rank = Param.Int(8, "");
     ranks_per_dimm = Param.Int(2, "");
@@ -53,3 +51,7 @@ class RubyMemoryControl(MemoryControl):
     tFaw = Param.Int(0, "");
     mem_random_arbitrate = Param.Int(0, "");
     mem_fixed_delay = Param.Cycles(0, "");
+
+    # single-ported on the system interface side, instantiate with a
+    # crossbar in front of the controller for multiple ports
+    port = SlavePort("Slave port")