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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-11-06 05:42:20 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-11-06 05:42:20 -0600 |
| commit | 85c29973a3cdbbbc2ed77014a730cbc625899b03 (patch) | |
| tree | 94dc98ea81cea698f2d9715f961f20bee70715e9 /src/mem/ruby/structures/SConscript | |
| parent | 95a0b184314cf0171a20fb7e71c845891dc56496 (diff) | |
| download | gem5-85c29973a3cdbbbc2ed77014a730cbc625899b03.tar.xz | |
ruby: remove sparse memory.
In my opinion, it creates needless complications in rest of the code.
Also, this structure hinders the move towards common set of code for
physical memory controllers.
Diffstat (limited to 'src/mem/ruby/structures/SConscript')
| -rw-r--r-- | src/mem/ruby/structures/SConscript | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mem/ruby/structures/SConscript b/src/mem/ruby/structures/SConscript index a5abbf449..dee5769d3 100644 --- a/src/mem/ruby/structures/SConscript +++ b/src/mem/ruby/structures/SConscript @@ -41,7 +41,6 @@ SimObject('RubyPrefetcher.py') SimObject('WireBuffer.py') Source('DirectoryMemory.cc') -Source('SparseMemory.cc') Source('CacheMemory.cc') Source('MemoryControl.cc') Source('WireBuffer.cc') |