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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-14 19:28:43 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-14 19:28:43 -0500 |
| commit | 5060e572ca07b98f7d84679bac81c0151dee46b9 (patch) | |
| tree | d7ff69a0fb7c5959b038dad87cd01e08801f33fe /src/mem/ruby/structures | |
| parent | b815221718d246549311b2923a2da7a233e1f625 (diff) | |
| download | gem5-5060e572ca07b98f7d84679bac81c0151dee46b9.tar.xz | |
ruby: call setMRU from L1 controllers, not from sequencer
Currently the sequencer calls the function setMRU that updates the replacement
policy structures with the first level caches. While functionally this is
correct, the problem is that this requires calling findTagInSet() which is an
expensive function. This patch removes the calls to setMRU from the sequencer.
All controllers should now update the replacement policy on their own.
The set and the way index for a given cache entry can be found within the
AbstractCacheEntry structure. Use these indicies to update the replacement
policy structures.
Diffstat (limited to 'src/mem/ruby/structures')
| -rw-r--r-- | src/mem/ruby/structures/CacheMemory.cc | 8 | ||||
| -rw-r--r-- | src/mem/ruby/structures/CacheMemory.hh | 2 |
2 files changed, 10 insertions, 0 deletions
diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc index ab2647759..931f58a8e 100644 --- a/src/mem/ruby/structures/CacheMemory.cc +++ b/src/mem/ruby/structures/CacheMemory.cc @@ -344,6 +344,14 @@ CacheMemory::setMRU(Addr address) } void +CacheMemory::setMRU(const AbstractCacheEntry *e) +{ + uint32_t cacheSet = e->getSetIndex(); + uint32_t loc = e->getWayIndex(); + m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); +} + +void CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const { uint64_t warmedUpBlocks = 0; diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh index 1af446950..7ce674e61 100644 --- a/src/mem/ruby/structures/CacheMemory.hh +++ b/src/mem/ruby/structures/CacheMemory.hh @@ -106,6 +106,8 @@ class CacheMemory : public SimObject // Set this address to most recently used void setMRU(Addr address); + // Set this entry to most recently used + void setMRU(const AbstractCacheEntry *e); // Functions for locking and unlocking cache lines corresponding to the // provided address. These are required for supporting atomic memory |