ruby: replace global g_system_ptr with per-object pointers

This is another step in the process of removing global variables
from Ruby to enable multiple RubySystem instances in a single simulation.

With possibly multiple RubySystem objects, we can no longer use a global
variable to find "the" RubySystem object.  Instead, each Ruby component
has to carry a pointer to the RubySystem object to which it belongs.

8 files changed, 22 insertions, 17 deletions

diff --git a/src/mem/ruby/structures/BankedArray.cc b/src/mem/ruby/structures/BankedArray.cc
index 0207f96be..dbde2ab9a 100644
--- a/src/mem/ruby/structures/BankedArray.cc
+++ b/src/mem/ruby/structures/BankedArray.cc
@@ -34,7 +34,8 @@
 #include "mem/ruby/system/System.hh"
 
 BankedArray::BankedArray(unsigned int banks, Cycles accessLatency,
-                         unsigned int startIndexBit)
+                         unsigned int startIndexBit, RubySystem *rs)
+    : m_ruby_system(rs)
 {
     this->banks = banks;
     this->accessLatency = accessLatency;
@@ -70,7 +71,7 @@ BankedArray::tryAccess(int64 idx)
     busyBanks[bank].idx = idx;
     busyBanks[bank].startAccess = curTick();
     busyBanks[bank].endAccess = curTick() +
-        (accessLatency-1) * g_system_ptr->clockPeriod();
+        (accessLatency-1) * m_ruby_system->clockPeriod();
 
     return true;
 }
diff --git a/src/mem/ruby/structures/BankedArray.hh b/src/mem/ruby/structures/BankedArray.hh
index ed9269eaa..5cc3eee32 100644
--- a/src/mem/ruby/structures/BankedArray.hh
+++ b/src/mem/ruby/structures/BankedArray.hh
@@ -35,6 +35,7 @@
 #include <vector>
 
 #include "mem/ruby/common/TypeDefines.hh"
+#include "mem/ruby/system/System.hh"
 #include "sim/core.hh"
 
 class BankedArray
@@ -44,6 +45,7 @@ class BankedArray
     Cycles accessLatency;
     unsigned int bankBits;
     unsigned int startIndexBit;
+    RubySystem *m_ruby_system;
 
     class AccessRecord
     {
@@ -62,7 +64,7 @@ class BankedArray
 
   public:
     BankedArray(unsigned int banks, Cycles accessLatency,
-                unsigned int startIndexBit);
+                unsigned int startIndexBit, RubySystem *rs);
 
     // Note: We try the access based on the cache index, not the address
     // This is so we don't get aliasing on blocks being replaced
diff --git a/src/mem/ruby/structures/Cache.py b/src/mem/ruby/structures/Cache.py
index c6e165e3a..3acec32cf 100644
--- a/src/mem/ruby/structures/Cache.py
+++ b/src/mem/ruby/structures/Cache.py
@@ -28,6 +28,7 @@
 #          Brad Beckmann
 
 from m5.params import *
+from m5.proxy import *
 from m5.SimObject import SimObject
 
 class RubyCache(SimObject):
@@ -46,3 +47,4 @@ class RubyCache(SimObject):
     dataAccessLatency = Param.Cycles(1, "cycles for a data array access")
     tagAccessLatency = Param.Cycles(1, "cycles for a tag array access")
     resourceStalls = Param.Bool(False, "stall if there is a resource failure")
+    ruby_system = Param.RubySystem(Parent.any, "")
diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc
index 9c17508a8..0576c4b33 100644
--- a/src/mem/ruby/structures/CacheMemory.cc
+++ b/src/mem/ruby/structures/CacheMemory.cc
@@ -53,8 +53,10 @@ RubyCacheParams::create()
 
 CacheMemory::CacheMemory(const Params *p)
     : SimObject(p),
-    dataArray(p->dataArrayBanks, p->dataAccessLatency, p->start_index_bit),
-    tagArray(p->tagArrayBanks, p->tagAccessLatency, p->start_index_bit)
+    dataArray(p->dataArrayBanks, p->dataAccessLatency,
+              p->start_index_bit, p->ruby_system),
+    tagArray(p->tagArrayBanks, p->tagAccessLatency,
+             p->start_index_bit, p->ruby_system)
 {
     m_cache_size = p->size;
     m_latency = p->latency;
diff --git a/src/mem/ruby/structures/RubyMemoryControl.cc b/src/mem/ruby/structures/RubyMemoryControl.cc
index 6e40d415c..6cd9bdf41 100644
--- a/src/mem/ruby/structures/RubyMemoryControl.cc
+++ b/src/mem/ruby/structures/RubyMemoryControl.cc
@@ -310,12 +310,6 @@ RubyMemoryControl::enqueueMemRef(MemoryNode *memRef)
     physical_address_t addr = memRef->m_addr;
     int bank = getBank(addr);
 
-    DPRINTF(RubyMemory,
-            "New memory request%7d: %#08x %c arrived at %10d bank = %3x sched %c\n",
-            m_msg_counter, addr, memRef->m_is_mem_read ? 'R':'W',
-            memRef->m_time * g_system_ptr->clockPeriod(),
-            bank, m_event.scheduled() ? 'Y':'N');
-
     m_profiler_ptr->profileMemReq(bank);
     m_input_queue.push_back(memRef);
 
diff --git a/src/mem/ruby/structures/WireBuffer.cc b/src/mem/ruby/structures/WireBuffer.cc
index 3308dbe8e..0375d9446 100644
--- a/src/mem/ruby/structures/WireBuffer.cc
+++ b/src/mem/ruby/structures/WireBuffer.cc
@@ -34,7 +34,6 @@
 
 #include "base/cprintf.hh"
 #include "base/stl_helpers.hh"
-#include "mem/ruby/common/Global.hh"
 #include "mem/ruby/structures/WireBuffer.hh"
 #include "mem/ruby/system/System.hh"
 
@@ -58,6 +57,7 @@ WireBuffer::WireBuffer(const Params *p)
     : SimObject(p)
 {
     m_msg_counter = 0;
+    m_ruby_system = p->ruby_system;
 }
 
 void
@@ -73,7 +73,7 @@ void
 WireBuffer::enqueue(MsgPtr message, Cycles latency)
 {
     m_msg_counter++;
-    Cycles current_time = g_system_ptr->curCycle();
+    Cycles current_time = m_ruby_system->curCycle();
     Cycles arrival_time = current_time + latency;
     assert(arrival_time > current_time);
 
@@ -82,7 +82,7 @@ WireBuffer::enqueue(MsgPtr message, Cycles latency)
     m_message_queue.push_back(message);
     if (m_consumer_ptr != NULL) {
         m_consumer_ptr->
-            scheduleEventAbsolute(g_system_ptr->clockPeriod() * arrival_time);
+            scheduleEventAbsolute(m_ruby_system->clockPeriod() * arrival_time);
     } else {
         panic("No Consumer for WireBuffer! %s\n", *this);
     }
@@ -116,12 +116,12 @@ WireBuffer::recycle()
     MsgPtr node = m_message_queue.front();
     pop_heap(m_message_queue.begin(), m_message_queue.end(), greater<MsgPtr>());
 
-    node->setLastEnqueueTime(g_system_ptr->curCycle() + Cycles(1));
+    node->setLastEnqueueTime(m_ruby_system->curCycle() + Cycles(1));
     m_message_queue.back() = node;
     push_heap(m_message_queue.begin(), m_message_queue.end(),
         greater<MsgPtr>());
     m_consumer_ptr->
-        scheduleEventAbsolute(g_system_ptr->curCycle() + Cycles(1));
+        scheduleEventAbsolute(m_ruby_system->curCycle() + Cycles(1));
 }
 
 bool
@@ -129,7 +129,7 @@ WireBuffer::isReady()
 {
     return ((!m_message_queue.empty()) &&
             (m_message_queue.front()->getLastEnqueueTime() <=
-                    g_system_ptr->curCycle()));
+                    m_ruby_system->curCycle()));
 }
 
 void
diff --git a/src/mem/ruby/structures/WireBuffer.hh b/src/mem/ruby/structures/WireBuffer.hh
index a724f1381..4282f524e 100644
--- a/src/mem/ruby/structures/WireBuffer.hh
+++ b/src/mem/ruby/structures/WireBuffer.hh
@@ -94,6 +94,8 @@ class WireBuffer : public SimObject
     // queues where memory requests live
     std::vector<MsgPtr> m_message_queue;
 
+    RubySystem * m_ruby_system;
+
 };
 
 std::ostream& operator<<(std::ostream& out, const WireBuffer& obj);
diff --git a/src/mem/ruby/structures/WireBuffer.py b/src/mem/ruby/structures/WireBuffer.py
index 441947adf..9a55390a2 100644
--- a/src/mem/ruby/structures/WireBuffer.py
+++ b/src/mem/ruby/structures/WireBuffer.py
@@ -27,9 +27,11 @@
 # Author: Lisa Hsu
 
 from m5.params import *
+from m5.proxy import *
 from m5.SimObject import SimObject
 
 class RubyWireBuffer(SimObject):
     type = 'RubyWireBuffer'
     cxx_class = 'WireBuffer'
     cxx_header = "mem/ruby/structures/WireBuffer.hh"
+    ruby_system = Param.RubySystem(Parent.any, "")