ruby: handle llsc accesses through CacheEntry, not CacheMemory

The sequencer takes care of llsc accesses by calling upon functions
from the CacheMemory.  This is unnecessary once the required CacheEntry object
is available.  Thus some of the calls to findTagInSet() are avoided.

2 files changed, 8 insertions, 3 deletions

diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc
index 7eba450c1..bb26ff03c 100644
--- a/src/mem/ruby/structures/CacheMemory.cc
+++ b/src/mem/ruby/structures/CacheMemory.cc
@@ -413,7 +413,7 @@ CacheMemory::setLocked(Addr address, int context)
     int64 cacheSet = addressToCacheSet(address);
     int loc = findTagInSet(cacheSet, address);
     assert(loc != -1);
-    m_cache[cacheSet][loc]->m_locked = context;
+    m_cache[cacheSet][loc]->setLocked(context);
 }
 
 void
@@ -424,7 +424,7 @@ CacheMemory::clearLocked(Addr address)
     int64 cacheSet = addressToCacheSet(address);
     int loc = findTagInSet(cacheSet, address);
     assert(loc != -1);
-    m_cache[cacheSet][loc]->m_locked = -1;
+    m_cache[cacheSet][loc]->clearLocked();
 }
 
 bool
@@ -436,7 +436,7 @@ CacheMemory::isLocked(Addr address, int context)
     assert(loc != -1);
     DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n",
             address, m_cache[cacheSet][loc]->m_locked, context);
-    return m_cache[cacheSet][loc]->m_locked == context;
+    return m_cache[cacheSet][loc]->isLocked(context);
 }
 
 void
diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh
index 08551ab87..6c719cb4f 100644
--- a/src/mem/ruby/structures/CacheMemory.hh
+++ b/src/mem/ruby/structures/CacheMemory.hh
@@ -107,6 +107,11 @@ class CacheMemory : public SimObject
     // Set this address to most recently used
     void setMRU(Addr address);
 
+    // Functions for locking and unlocking cache lines corresponding to the
+    // provided address.  These are required for supporting atomic memory
+    // accesses.  These are to be used when only the address of the cache entry
+    // is available.  In case the entry itself is available. use the functions
+    // provided by the AbstractCacheEntry class.
     void setLocked (Addr addr, int context);
     void clearLocked (Addr addr);
     bool isLocked (Addr addr, int context);