diff options
| author | Akash Bagdia <akash.bagdia@ARM.com> | 2014-11-18 14:00:48 +0000 |
|---|---|---|
| committer | Akash Bagdia <akash.bagdia@ARM.com> | 2014-11-18 14:00:48 +0000 |
| commit | 3ee4957b4930a252c0185a6bc71bdf1c6ebc5ed9 (patch) | |
| tree | 6a7e1807397f002f51fddb34568b89250fca45c8 /src/mem/ruby/structures | |
| parent | 65ecd954861aa76532ca79453afcf66a837e1fa6 (diff) | |
| download | gem5-3ee4957b4930a252c0185a6bc71bdf1c6ebc5ed9.tar.xz | |
power: Add power states to ClockedObject
Add 4 power states to the ClockedObject, provides necessary access functions
to check and update the power state. Default power state is UNDEFINED, it is
responsibility of the respective simulation model to provide the startup state
and any other logic for state change.
Add number of transition stat.
Add distribution of time spent in clock gated state.
Add power state residency stat.
Add dump call back function to allow stats update of distribution and residency
stats.
Diffstat (limited to 'src/mem/ruby/structures')
| -rw-r--r-- | src/mem/ruby/structures/CacheMemory.cc | 2 | ||||
| -rw-r--r-- | src/mem/ruby/structures/Prefetcher.cc | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc index f7c196119..36d109769 100644 --- a/src/mem/ruby/structures/CacheMemory.cc +++ b/src/mem/ruby/structures/CacheMemory.cc @@ -488,6 +488,8 @@ CacheMemory::isLocked(Addr address, int context) void CacheMemory::regStats() { + SimObject::regStats(); + m_demand_hits .name(name() + ".demand_hits") .desc("Number of cache demand hits") diff --git a/src/mem/ruby/structures/Prefetcher.cc b/src/mem/ruby/structures/Prefetcher.cc index ce6d36c04..eef51dcf7 100644 --- a/src/mem/ruby/structures/Prefetcher.cc +++ b/src/mem/ruby/structures/Prefetcher.cc @@ -86,6 +86,8 @@ Prefetcher::~Prefetcher() void Prefetcher::regStats() { + SimObject::regStats(); + numMissObserved .name(name() + ".miss_observed") .desc("number of misses observed") |