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| author | Brandon Potter <brandon.potter@amd.com> | 2015-07-10 16:05:23 -0500 |
|---|---|---|
| committer | Brandon Potter <brandon.potter@amd.com> | 2015-07-10 16:05:23 -0500 |
| commit | 9eda4bdc5a947883a2d55ab860d37c5cd80c3370 (patch) | |
| tree | 0dc23e2bdca0338129ba473e259f891a2edb15c1 /src/mem/ruby/structures | |
| parent | a74c446e7d034cebe01babb92f448a145b4ba77d (diff) | |
| download | gem5-9eda4bdc5a947883a2d55ab860d37c5cd80c3370.tar.xz | |
ruby: remove extra whitespace and correct misspelled words
Diffstat (limited to 'src/mem/ruby/structures')
| -rw-r--r-- | src/mem/ruby/structures/BankedArray.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mem/ruby/structures/BankedArray.hh b/src/mem/ruby/structures/BankedArray.hh index 7cc6563d4..ed9269eaa 100644 --- a/src/mem/ruby/structures/BankedArray.hh +++ b/src/mem/ruby/structures/BankedArray.hh @@ -61,7 +61,8 @@ class BankedArray unsigned int mapIndexToBank(int64 idx); public: - BankedArray(unsigned int banks, Cycles accessLatency, unsigned int startIndexBit); + BankedArray(unsigned int banks, Cycles accessLatency, + unsigned int startIndexBit); // Note: We try the access based on the cache index, not the address // This is so we don't get aliasing on blocks being replaced |